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Tue, 26 Nov 2024 06:01:56 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b01e1046sm234743975e9.4.2024.11.26.06.01.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:01:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 16/16] target/mips: Convert nanoMIPS LI opcodes to decodetree Date: Tue, 26 Nov 2024 15:00:02 +0100 Message-ID: <20241126140003.74871-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/nanomips16.decode | 8 ++++++++ target/mips/tcg/nanomips48.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 21 +++++++++++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 17 ----------------- 4 files changed, 37 insertions(+), 17 deletions(-) diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode index 81fdc68e98b..12815161d9c 100644 --- a/target/mips/tcg/nanomips16.decode +++ b/target/mips/tcg/nanomips16.decode @@ -6,3 +6,11 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&rd_imm rd imm not_in_nms + +%s_eu 0:s7 !function=s_eu + +@rt3_s ...... rd:3 ....... &rd_imm imm=%s_eu + +LI 110100 ... ....... @rt3_s not_in_nms=0 # LI[16] diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode index 696cc15607a..778bff4ec06 100644 --- a/target/mips/tcg/nanomips48.decode +++ b/target/mips/tcg/nanomips48.decode @@ -6,3 +6,11 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&rd_imm rd imm not_in_nms !extern + +%imm 16:16 0:s16 + +@rd_imm ...... rd:5 ..... ................ ................ &rd_imm imm=%imm + +LI 011000 ..... 00000 ................ ................ @rd_imm not_in_nms=1 diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c index 3e77fcd23d3..aee0606e4d4 100644 --- a/target/mips/tcg/nanomips_translate.c +++ b/target/mips/tcg/nanomips_translate.c @@ -9,14 +9,35 @@ #include "qemu/osdep.h" #include "translate.h" +static inline int s_eu(DisasContext *ctx, int x) +{ + return x == 0x7f ? -1 : x; +} + /* Include the auto-generated decoders. */ #include "decode-nanomips16.c.inc" #include "decode-nanomips32.c.inc" #include "decode-nanomips48.c.inc" +static inline void check_nms(DisasContext *ctx, bool not_in_nms) +{ + if (not_in_nms && unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { + gen_reserved_instruction(ctx); + } +} + static bool trans_LSA(DisasContext *ctx, arg_r *a) { gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); return true; } + +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a) +{ + check_nms(ctx, a->not_in_nms); + + gen_li(ctx, a->rd, a->imm); + + return true; +} diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 0627f01c19e..e3d81d9e15b 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -57,7 +57,6 @@ enum { NM_POOL32S = 0x30, NM_P_BRI = 0x32, - NM_LI16 = 0x34, NM_SWGP16 = 0x35, NM_P16_BR = 0x36, @@ -86,7 +85,6 @@ enum { /* P48I instruction pool */ enum { - NM_LI48 = 0x00, NM_ADDIU48 = 0x01, NM_ADDIUGP48 = 0x02, NM_ADDIUPC48 = 0x03, @@ -3664,12 +3662,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { - case NM_LI48: - check_nms(ctx); - if (rt != 0) { - tcg_gen_movi_tl(cpu_gpr[rt], addr_off); - } - break; case NM_ADDIU48: check_nms(ctx); if (rt != 0) { @@ -4620,15 +4612,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) break; } break; - case NM_LI16: - { - imm = extract32(ctx->opcode, 0, 7); - imm = (imm == 0x7f ? -1 : imm); - if (rt != 0) { - tcg_gen_movi_tl(cpu_gpr[rt], imm); - } - } - break; case NM_ANDI16: { uint32_t u = extract32(ctx->opcode, 0, 4);