| Message ID | 20241126140003.74871-8-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Convert nanoMIPS LSA opcode to decodetree | expand |
On 11/26/24 07:59, Philippe Mathieu-Daudé wrote: > Introduce the MIPS16e decodetree configs for the 16-bit > and 32-bit instructions. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/tcg/translate.h | 2 ++ > target/mips/tcg/mips16e_16.decode | 9 +++++++++ > target/mips/tcg/mips16e_32.decode | 9 +++++++++ > target/mips/tcg/mips16e_translate.c | 14 ++++++++++++++ > target/mips/tcg/mips16e_translate.c.inc | 8 ++++++++ > target/mips/tcg/meson.build | 3 +++ > 6 files changed, 45 insertions(+) > create mode 100644 target/mips/tcg/mips16e_16.decode > create mode 100644 target/mips/tcg/mips16e_32.decode > create mode 100644 target/mips/tcg/mips16e_translate.c > > diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h > index a65ab4a747c..d1aa811cfa1 100644 > --- a/target/mips/tcg/translate.h > +++ b/target/mips/tcg/translate.h > @@ -223,6 +223,8 @@ bool decode_64bit_enabled(DisasContext *ctx); > > /* decodetree generated */ > bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); > +bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); > +bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); > bool decode_ase_msa(DisasContext *ctx, uint32_t insn); > bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); > bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); > diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode > new file mode 100644 > index 00000000000..82586493f68 > --- /dev/null > +++ b/target/mips/tcg/mips16e_16.decode > @@ -0,0 +1,9 @@ > +# MIPS16e 16-bit instruction set extensions > +# > +# Copyright (C) 2021 Philippe Mathieu-Daudé > +# > +# SPDX-License-Identifier: LGPL-2.1-or-later > +# > +# Reference: MIPS Architecture for Programmers, Volume IV-a > +# The MIPS16e Application Specific Extension > +# (Document Number: MD00076) > diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode > new file mode 100644 > index 00000000000..fc429049e18 > --- /dev/null > +++ b/target/mips/tcg/mips16e_32.decode > @@ -0,0 +1,9 @@ > +# MIPS16e 32-bit instruction set extensions > +# > +# Copyright (C) 2021 Philippe Mathieu-Daudé > +# > +# SPDX-License-Identifier: LGPL-2.1-or-later > +# > +# Reference: MIPS Architecture for Programmers, Volume IV-a > +# The MIPS16e Application Specific Extension > +# (Document Number: MD00076) > diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c > new file mode 100644 > index 00000000000..6de9928b37e > --- /dev/null > +++ b/target/mips/tcg/mips16e_translate.c > @@ -0,0 +1,14 @@ > +/* > + * MIPS emulation for QEMU - MIPS16e translation routines > + * > + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "translate.h" > + > +/* Include the auto-generated decoders. */ > +#include "decode-mips16e_16.c.inc" > +#include "decode-mips16e_32.c.inc" > diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc > index defef3ce559..a57ae4e95b1 100644 > --- a/target/mips/tcg/mips16e_translate.c.inc > +++ b/target/mips/tcg/mips16e_translate.c.inc > @@ -657,6 +657,14 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) > int n_bytes; > > ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); > + > + if (decode_ase_mips16e_16(ctx, ctx->opcode)) { > + return 2; > + } > + if (decode_ase_mips16e_32(ctx, ctx->opcode)) { > + return 4; > + } This is misplaced wrt loading 32-bits of opcode. You have two options: opcode = lduw(...) if (extract32(opcode, 11, 5) == M16_OPC_EXTEND) { opcode <<= 16; opcode |= lduw(...); decode_ase_mips16e_32(...); } else { decode_ase_mips16e_16(...); } Or, make use of the variable-length support in decodetree. Given the trivial test above, the complexity and oddness of the variable-length stuff doesn't seem worth it. r~
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index a65ab4a747c..d1aa811cfa1 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -223,6 +223,8 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); +bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); +bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode new file mode 100644 index 00000000000..82586493f68 --- /dev/null +++ b/target/mips/tcg/mips16e_16.decode @@ -0,0 +1,9 @@ +# MIPS16e 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode new file mode 100644 index 00000000000..fc429049e18 --- /dev/null +++ b/target/mips/tcg/mips16e_32.decode @@ -0,0 +1,9 @@ +# MIPS16e 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c new file mode 100644 index 00000000000..6de9928b37e --- /dev/null +++ b/target/mips/tcg/mips16e_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - MIPS16e translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org> + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-mips16e_16.c.inc" +#include "decode-mips16e_32.c.inc" diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index defef3ce559..a57ae4e95b1 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -657,6 +657,14 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) int n_bytes; ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); + + if (decode_ase_mips16e_16(ctx, ctx->opcode)) { + return 2; + } + if (decode_ase_mips16e_32(ctx, ctx->opcode)) { + return 4; + } + op = (ctx->opcode >> 11) & 0x1f; sa = (ctx->opcode >> 2) & 0x7; sa = sa == 0 ? 8 : sa; diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7b18e6c4c8b..bcb64368be8 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen = [ + decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']), + decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -16,6 +18,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', 'op_helper.c',
Introduce the MIPS16e decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/mips16e_16.decode | 9 +++++++++ target/mips/tcg/mips16e_32.decode | 9 +++++++++ target/mips/tcg/mips16e_translate.c | 14 ++++++++++++++ target/mips/tcg/mips16e_translate.c.inc | 8 ++++++++ target/mips/tcg/meson.build | 3 +++ 6 files changed, 45 insertions(+) create mode 100644 target/mips/tcg/mips16e_16.decode create mode 100644 target/mips/tcg/mips16e_32.decode create mode 100644 target/mips/tcg/mips16e_translate.c