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Tue, 26 Nov 2024 06:00:50 -0800 (PST) Received: from localhost.localdomain ([176.176.143.205]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fafeceesm13407142f8f.37.2024.11.26.06.00.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 26 Nov 2024 06:00:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH v3 07/16] target/mips: Introduce decode tree bindings for MIPS16e ASE Date: Tue, 26 Nov 2024 14:59:53 +0100 Message-ID: <20241126140003.74871-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126140003.74871-1-philmd@linaro.org> References: <20241126140003.74871-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce the MIPS16e decodetree configs for the 16-bit and 32-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/mips16e_16.decode | 9 +++++++++ target/mips/tcg/mips16e_32.decode | 9 +++++++++ target/mips/tcg/mips16e_translate.c | 14 ++++++++++++++ target/mips/tcg/mips16e_translate.c.inc | 8 ++++++++ target/mips/tcg/meson.build | 3 +++ 6 files changed, 45 insertions(+) create mode 100644 target/mips/tcg/mips16e_16.decode create mode 100644 target/mips/tcg/mips16e_32.decode create mode 100644 target/mips/tcg/mips16e_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index a65ab4a747c..d1aa811cfa1 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -223,6 +223,8 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); +bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); +bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode new file mode 100644 index 00000000000..82586493f68 --- /dev/null +++ b/target/mips/tcg/mips16e_16.decode @@ -0,0 +1,9 @@ +# MIPS16e 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode new file mode 100644 index 00000000000..fc429049e18 --- /dev/null +++ b/target/mips/tcg/mips16e_32.decode @@ -0,0 +1,9 @@ +# MIPS16e 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c new file mode 100644 index 00000000000..6de9928b37e --- /dev/null +++ b/target/mips/tcg/mips16e_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - MIPS16e translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-mips16e_16.c.inc" +#include "decode-mips16e_32.c.inc" diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index defef3ce559..a57ae4e95b1 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -657,6 +657,14 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) int n_bytes; ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); + + if (decode_ase_mips16e_16(ctx, ctx->opcode)) { + return 2; + } + if (decode_ase_mips16e_32(ctx, ctx->opcode)) { + return 4; + } + op = (ctx->opcode >> 11) & 0x1f; sa = (ctx->opcode >> 2) & 0x7; sa = sa == 0 ? 8 : sa; diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7b18e6c4c8b..bcb64368be8 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen = [ + decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']), + decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -16,6 +18,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', 'op_helper.c',