diff mbox series

[28/67] target/arm: Convert BFCVT to decodetree

Message ID 20241201150607.12812-29-richard.henderson@linaro.org (mailing list archive)
State New
Headers show
Series target/arm: AArch64 decodetree conversion, final part | expand

Commit Message

Richard Henderson Dec. 1, 2024, 3:05 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-a64.c | 24 ++++++------------------
 target/arm/tcg/a64.decode      |  3 +++
 2 files changed, 9 insertions(+), 18 deletions(-)

Comments

Peter Maydell Dec. 3, 2024, 2:05 p.m. UTC | #1 
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/tcg/translate-a64.c | 24 ++++++------------------
>  target/arm/tcg/a64.decode      |  3 +++
>  2 files changed, 9 insertions(+), 18 deletions(-)
>
> @@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
>          break;
>
>      case 0x6:
> -        switch (type) {
> -        case 1: /* BFCVT */

Here we decode BFCVT when the 'ftype' field (bits [23:22]) is 0b01...

> -            if (!dc_isar_feature(aa64_bf16, s)) {
> -                goto do_unallocated;
> -            }
> -            if (!fp_access_check(s)) {
> -                return;
> -            }
> -            handle_fp_1src_single(s, opcode, rd, rn);
> -            break;
> -        default:
> -            goto do_unallocated;
> -        }
> -        break;
> -
>      default:
>      do_unallocated:
>          unallocated_encoding(s);
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index fbfdf96eb3..476989c1b4 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -45,6 +45,7 @@
>  &qrrrr_e        q rd rn rm ra esz
>
>  @rr_h           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=1
> +@rr_s           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=2
>  @rr_d           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=3
>  @rr_sd          ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_sd
>  @rr_hsd         ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_hsd
> @@ -1337,6 +1338,8 @@ FRINTA_s        00011110 .. 1 001100 10000 ..... .....      @rr_hsd
>  FRINTX_s        00011110 .. 1 001110 10000 ..... .....      @rr_hsd
>  FRINTI_s        00011110 .. 1 001111 10000 ..... .....      @rr_hsd
>
> +BFCVT_s         00011110 10 1 000110 10000 ..... .....      @rr_s

...but this decode pattern has them as 0b10.


--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1338,7 +1338,7 @@ FRINTA_s        00011110 .. 1 001100 10000 .....
.....      @rr_hsd
 FRINTX_s        00011110 .. 1 001110 10000 ..... .....      @rr_hsd
 FRINTI_s        00011110 .. 1 001111 10000 ..... .....      @rr_hsd

-BFCVT_s         00011110 10 1 000110 10000 ..... .....      @rr_s
+BFCVT_s         00011110 01 1 000110 10000 ..... .....      @rr_s

 # Floating-point Immediate

should fix this.

thanks
-- PMM
Richard Henderson Dec. 3, 2024, 3:28 p.m. UTC | #2 
On 12/3/24 08:05, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:11, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/arm/tcg/translate-a64.c | 24 ++++++------------------
>>   target/arm/tcg/a64.decode      |  3 +++
>>   2 files changed, 9 insertions(+), 18 deletions(-)
>>
>> @@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
>>           break;
>>
>>       case 0x6:
>> -        switch (type) {
>> -        case 1: /* BFCVT */
> 
> Here we decode BFCVT when the 'ftype' field (bits [23:22]) is 0b01...
> 
>> -            if (!dc_isar_feature(aa64_bf16, s)) {
>> -                goto do_unallocated;
>> -            }
>> -            if (!fp_access_check(s)) {
>> -                return;
>> -            }
>> -            handle_fp_1src_single(s, opcode, rd, rn);
>> -            break;
>> -        default:
>> -            goto do_unallocated;
>> -        }
>> -        break;
>> -
>>       default:
>>       do_unallocated:
>>           unallocated_encoding(s);
>> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
>> index fbfdf96eb3..476989c1b4 100644
>> --- a/target/arm/tcg/a64.decode
>> +++ b/target/arm/tcg/a64.decode
>> @@ -45,6 +45,7 @@
>>   &qrrrr_e        q rd rn rm ra esz
>>
>>   @rr_h           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=1
>> +@rr_s           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=2
>>   @rr_d           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=3
>>   @rr_sd          ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_sd
>>   @rr_hsd         ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_hsd
>> @@ -1337,6 +1338,8 @@ FRINTA_s        00011110 .. 1 001100 10000 ..... .....      @rr_hsd
>>   FRINTX_s        00011110 .. 1 001110 10000 ..... .....      @rr_hsd
>>   FRINTI_s        00011110 .. 1 001111 10000 ..... .....      @rr_hsd
>>
>> +BFCVT_s         00011110 10 1 000110 10000 ..... .....      @rr_s
> 
> ...but this decode pattern has them as 0b10.
> 
> 
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -1338,7 +1338,7 @@ FRINTA_s        00011110 .. 1 001100 10000 .....
> .....      @rr_hsd
>   FRINTX_s        00011110 .. 1 001110 10000 ..... .....      @rr_hsd
>   FRINTI_s        00011110 .. 1 001111 10000 ..... .....      @rr_hsd
> 
> -BFCVT_s         00011110 10 1 000110 10000 ..... .....      @rr_s
> +BFCVT_s         00011110 01 1 000110 10000 ..... .....      @rr_s
> 
>   # Floating-point Immediate
> 
> should fix this.

Yep, thanks.  Fixed.


r~
diff mbox series

Patch

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index e8842012ea..b713c7d184 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8424,6 +8424,11 @@  static const FPScalar1 f_scalar_frintx = {
 };
 TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1)
 
+static const FPScalar1 f_scalar_bfcvt = {
+    .gen_s = gen_helper_bfcvt,
+};
+TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar, a, &f_scalar_bfcvt, -1)
+
 /* Floating-point data-processing (1 source) - single precision */
 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
 {
@@ -8436,9 +8441,6 @@  static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
     tcg_res = tcg_temp_new_i32();
 
     switch (opcode) {
-    case 0x6: /* BFCVT */
-        gen_fpst = gen_helper_bfcvt;
-        break;
     case 0x10: /* FRINT32Z */
         rmode = FPROUNDING_ZERO;
         gen_fpst = gen_helper_frint32_s;
@@ -8458,6 +8460,7 @@  static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
     case 0x1: /* FABS */
     case 0x2: /* FNEG */
     case 0x3: /* FSQRT */
+    case 0x6: /* BFCVT */
     case 0x8: /* FRINTN */
     case 0x9: /* FRINTP */
     case 0xa: /* FRINTM */
@@ -8661,21 +8664,6 @@  static void disas_fp_1src(DisasContext *s, uint32_t insn)
         break;
 
     case 0x6:
-        switch (type) {
-        case 1: /* BFCVT */
-            if (!dc_isar_feature(aa64_bf16, s)) {
-                goto do_unallocated;
-            }
-            if (!fp_access_check(s)) {
-                return;
-            }
-            handle_fp_1src_single(s, opcode, rd, rn);
-            break;
-        default:
-            goto do_unallocated;
-        }
-        break;
-
     default:
     do_unallocated:
         unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fbfdf96eb3..476989c1b4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -45,6 +45,7 @@ 
 &qrrrr_e        q rd rn rm ra esz
 
 @rr_h           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=1
+@rr_s           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=2
 @rr_d           ........ ... ..... ...... rn:5 rd:5     &rr_e esz=3
 @rr_sd          ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_sd
 @rr_hsd         ........ ... ..... ...... rn:5 rd:5     &rr_e esz=%esz_hsd
@@ -1337,6 +1338,8 @@  FRINTA_s        00011110 .. 1 001100 10000 ..... .....      @rr_hsd
 FRINTX_s        00011110 .. 1 001110 10000 ..... .....      @rr_hsd
 FRINTI_s        00011110 .. 1 001111 10000 ..... .....      @rr_hsd
 
+BFCVT_s         00011110 10 1 000110 10000 ..... .....      @rr_s
+
 # Floating-point Immediate
 
 FMOVI_s         0001 1110 .. 1 imm:8 100 00000 rd:5         esz=%esz_hsd