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Thu, 05 Dec 2024 12:00:37 -0800 (PST) Date: Thu, 5 Dec 2024 20:00:22 +0000 In-Reply-To: <20241205200025.2081863-1-whendrik@google.com> Mime-Version: 1.0 References: <20241205200025.2081863-1-whendrik@google.com> X-Mailer: git-send-email 2.47.0.338.g60cca15819-goog Message-ID: <20241205200025.2081863-6-whendrik@google.com> Subject: [PATCH v4 5/8] i386: Add CPUID enumeration for RDT From: Hendrik Wuethrich To: qemu-devel@nongnu.org, eduardo@habkost.net, richard.henderson@linaro.org, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com Cc: peternewman@google.com, " =?utf-8?b?4oCqSGVuZHJpayBXw7x0aHJpY2g=?= " Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=3ZQZSZwgKCvoyjgpftkmiqqing.eqosgow-fgxgnpqpipw.qti@flex--whendrik.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -100 X-Spam_score: -10.1 X-Spam_bar: ---------- X-Spam_report: (-10.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.453, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: ‪Hendrik Wüthrich Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wüthrich --- hw/i386/rdt.c | 30 ++++++++++++++++++ include/hw/i386/rdt.h | 31 +++++++++++++++++++ target/i386/cpu.c | 71 +++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 5 +++ 4 files changed, 137 insertions(+) diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c index 3a37341bd6..1409f9a904 100644 --- a/hw/i386/rdt.c +++ b/hw/i386/rdt.c @@ -35,6 +35,17 @@ #define RDT_MAX_L2_MASK_COUNT 63 #define RDT_MAX_MBA_THRTL_COUNT 63 +/* RDT L3 Allocation features */ +#define CPUID_10_1_EAX_CBM_LENGTH 0xf +#define CPUID_10_1_EBX_CBM 0x0 +#define CPUID_10_1_ECX_CDP 0x0 // to enable, it would be (1U << 2) +/* RDT L2 Allocation features*/ +#define CPUID_10_2_EAX_CBM_LENGTH 0xf +#define CPUID_10_2_EBX_CBM 0x0 +/* RDT MBA features */ +#define CPUID_10_3_EAX_THRTL_MAX 89 +#define CPUID_10_3_ECX_LINEAR_RESPONSE (1U << 2) + #define TYPE_RDT "rdt" #define RDT_NUM_RMID_PROP "rmids" @@ -81,8 +92,27 @@ struct RDTState { struct RDTStateClass { }; +uint32_t rdt_get_cpuid_15_0_edx_l3(void) { return CPUID_15_1_EDX_L3_OCCUPANCY | CPUID_15_1_EDX_L3_TOTAL_BW | CPUID_15_1_EDX_L3_LOCAL_BW; } + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void) { return CPUID_15_1_EDX_L3_TOTAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void) { return CPUID_15_1_EDX_L3_LOCAL_BW; } +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void) { return CPUID_15_1_EDX_L3_OCCUPANCY; } + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void) { return CPUID_10_0_EBX_L3_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void) { return CPUID_10_0_EBX_L2_CAT; } +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void) { return CPUID_10_0_EBX_MBA; } + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void) { return CPUID_10_1_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void) { return CPUID_10_1_EBX_CBM; } +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void) { return CPUID_10_1_ECX_CDP; } uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COUNT; } + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void) { return CPUID_10_2_EAX_CBM_LENGTH; } +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void) { return CPUID_10_2_EBX_CBM; } uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COUNT; } + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void) { return CPUID_10_3_EAX_THRTL_MAX; } +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void) { return CPUID_10_3_ECX_LINEAR_RESPONSE; } uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return RDT_MAX_MBA_THRTL_COUNT; } bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h index ec82a149f2..57d2fa5b77 100644 --- a/include/hw/i386/rdt.h +++ b/include/hw/i386/rdt.h @@ -20,13 +20,44 @@ #include #include +/* RDT L3 Cache Monitoring Technology */ +#define CPUID_15_0_EDX_L3 (1U << 1) +#define CPUID_15_1_EDX_L3_OCCUPANCY (1U << 0) +#define CPUID_15_1_EDX_L3_TOTAL_BW (1U << 1) +#define CPUID_15_1_EDX_L3_LOCAL_BW (1U << 2) + +/* RDT Cache Allocation Technology */ +#define CPUID_10_0_EBX_L3_CAT (1U << 1) +#define CPUID_10_0_EBX_L2_CAT (1U << 2) +#define CPUID_10_0_EBX_MBA (1U << 3) +#define CPUID_10_0_EDX CPUID_10_0_EBX_L3_CAT | CPUID_10_0_EBX_L2_CAT | CPUID_10_0_EBX_MBA + typedef struct RDTState RDTState; typedef struct RDTStatePerCore RDTStatePerCore; typedef struct RDTMonitor RDTMonitor; typedef struct RDTAllocation RDTAllocation; +uint32_t rdt_get_cpuid_15_0_edx_l3(void); + +uint32_t rdt_cpuid_15_1_edx_l3_total_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_local_bw_enabled(void); +uint32_t rdt_cpuid_15_1_edx_l3_occupancy_enabled(void); + +uint32_t rdt_cpuid_10_0_ebx_l3_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_cat_enabled(void); +uint32_t rdt_cpuid_10_0_ebx_l2_mba_enabled(void); + +uint32_t rdt_get_cpuid_10_1_eax_cbm_length(void); +uint32_t rdt_cpuid_10_1_ebx_cbm_enabled(void); +uint32_t rdt_cpuid_10_1_ecx_cdp_enabled(void); uint32_t rdt_get_cpuid_10_1_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_2_eax_cbm_length(void); +uint32_t rdt_cpuid_10_2_ebx_cbm_enabled(void); uint32_t rdt_get_cpuid_10_2_edx_cos_max(void); + +uint32_t rdt_get_cpuid_10_3_eax_thrtl_max(void); +uint32_t rdt_cpuid_10_3_eax_linear_response_enabled(void); uint32_t rdt_get_cpuid_10_3_edx_cos_max(void); bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3725dbbc4b..bbe2da8ebb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -41,6 +41,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "hw/i386/rdt.h" #include "disas/capstone.h" #include "cpu-internal.h" @@ -6725,6 +6726,76 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, assert(!(*eax & ~0x1f)); *ebx &= 0xffff; /* The count doesn't need to be reliable. */ break; +#ifndef CONFIG_USER_ONLY + case 0xF: + /* Shared Resource Monitoring Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQM)) + break; + if (!(cpu->rdt)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Monitoring Resource Type Enumeration */ + case 0: + *edx = env->features[FEAT_RDT_15_0_EDX]; + *ebx = rdt_max_rmid(cpu->rdt); + break; + case 1: + *ebx = 1; + *ecx = rdt_max_rmid(cpu->rdt); + *edx = rdt_cpuid_15_1_edx_l3_total_bw_enabled() | + rdt_cpuid_15_1_edx_l3_local_bw_enabled() | + rdt_cpuid_15_1_edx_l3_occupancy_enabled(); + break; + } + break; + case 0x10: + /* Shared Resource Director Technology Allocation Enumeration Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_PQE)) + break; + if (!(cpu->rdt)) { + warn_report("Intel RDT features enabled in commandline, " + "but rdt device not used"); + break; + } + /* Non-zero count is ResId */ + switch (count) { + /* Cache Allocation Technology Available Resource Types */ + case 0: + *ebx |= rdt_cpuid_10_0_ebx_l3_cat_enabled(); + *ebx |= rdt_cpuid_10_0_ebx_l2_cat_enabled(); + *ebx |= rdt_cpuid_10_0_ebx_l2_mba_enabled(); + break; + case 1: + *eax = rdt_get_cpuid_10_1_eax_cbm_length(); + *ebx = rdt_cpuid_10_1_ebx_cbm_enabled(); + *ecx |= rdt_cpuid_10_1_ecx_cdp_enabled(); + *edx = rdt_get_cpuid_10_1_edx_cos_max(); + break; + case 2: + *eax = rdt_get_cpuid_10_2_eax_cbm_length(); + *ebx = rdt_cpuid_10_2_ebx_cbm_enabled(); + *edx = rdt_get_cpuid_10_2_edx_cos_max(); + break; + case 3: + *eax = rdt_get_cpuid_10_3_eax_thrtl_max(); + *ecx = rdt_cpuid_10_3_eax_linear_response_enabled(); + *edx = rdt_get_cpuid_10_3_edx_cos_max(); + break; + } + break; +#endif case 0x1C: if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 64a53efa30..98407c8e18 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -678,6 +678,7 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ + FEAT_RDT_15_0_EDX, /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */ FEATURE_WORDS, } FeatureWord; @@ -852,8 +853,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_EBX_RTM (1U << 11) /* Zero out FPU CS and FPU DS */ #define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13) +/* Resource Director Technology Monitoring */ +#define CPUID_7_0_EBX_PQM (1U << 12) /* Memory Protection Extension */ #define CPUID_7_0_EBX_MPX (1U << 14) +/* Resource Director Technology Allocation */ +#define CPUID_7_0_EBX_PQE (1U << 15) /* AVX-512 Foundation */ #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Doubleword & Quadword Instruction */