@@ -147,8 +147,8 @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
-DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
-DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
+DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
+DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
@@ -8502,8 +8502,9 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64();
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
write_fp_dreg(s, a->rd, tcg_rd);
}
return true;
@@ -8528,8 +8529,9 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) {
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32();
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
write_fp_sreg(s, a->rd, tcg_rd);
}
return true;
@@ -9208,7 +9210,9 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+
+ gen_helper_vfp_fcvtsd(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp);
}
@@ -9498,11 +9502,13 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
* The only instruction like this is FCVTL.
*/
int pass;
+ TCGv_ptr fpst;
if (!fp_access_check(s)) {
return true;
}
+ fpst = fpstatus_ptr(FPST_FPCR);
if (a->esz == MO_64) {
/* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2];
@@ -9512,7 +9518,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
for (pass = 0; pass < 2; pass++) {
tcg_res[pass] = tcg_temp_new_i64();
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
- gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
+ gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
@@ -9521,7 +9527,6 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
/* 16 -> 32 bit fp conversion */
int srcelt = a->q ? 4 : 0;
TCGv_i32 tcg_res[4];
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
TCGv_i32 ahp = get_ahp_flag();
for (pass = 0; pass < 4; pass++) {
@@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, tcg_env);
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg64(vd, a->vd);
return true;
}
@@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, tcg_env);
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg32(vd, a->vd);
return true;
}
@@ -400,14 +400,14 @@ FLOAT_CONVS(ui, d, float64, 64, u)
#undef FLOAT_CONVS
/* floating point conversion */
-float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
+float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
{
- return float32_to_float64(x, &env->vfp.fp_status);
+ return float32_to_float64(x, status);
}
-float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
+float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
{
- return float64_to_float32(x, &env->vfp.fp_status);
+ return float64_to_float32(x, status);
}
uint32_t HELPER(bfcvt)(float32 x, float_status *status)
Pass float_status not env to match other functions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate-a64.c | 15 ++++++++++----- target/arm/tcg/translate-vfp.c | 4 ++-- target/arm/vfp_helper.c | 8 ++++---- 4 files changed, 18 insertions(+), 13 deletions(-)