| Message ID | 20241210161733.1830573-24-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: AArch64 decodetree conversion, final part | expand |
On Tue, 10 Dec 2024 at 16:19, Richard Henderson <richard.henderson@linaro.org> wrote: > > These opcodes are only supported as vector operations, > not as advsimd scalar. Set only_in_vector, and remove > the unreachable implementation of scalar fneg. > > Reported-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/tcg/translate-a64.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index a99f3d0d13..f67360c4c5 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -10816,6 +10816,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) > break; > case 0x2f: /* FABS */ > case 0x6f: /* FNEG */ > + only_in_vector = true; > need_fpst = false; > break; > case 0x7d: /* FRSQRTE */ Also case 0x7f FRSQRT I think, which will currently fall into a g_assert_not_reached() for the scalar case. thanks -- PMM
On 12/11/24 09:44, Peter Maydell wrote: > On Tue, 10 Dec 2024 at 16:19, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> These opcodes are only supported as vector operations, >> not as advsimd scalar. Set only_in_vector, and remove >> the unreachable implementation of scalar fneg. >> >> Reported-by: Peter Maydell <peter.maydell@linaro.org> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/tcg/translate-a64.c | 4 +--- >> 1 file changed, 1 insertion(+), 3 deletions(-) >> >> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c >> index a99f3d0d13..f67360c4c5 100644 >> --- a/target/arm/tcg/translate-a64.c >> +++ b/target/arm/tcg/translate-a64.c >> @@ -10816,6 +10816,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) >> break; >> case 0x2f: /* FABS */ >> case 0x6f: /* FNEG */ >> + only_in_vector = true; >> need_fpst = false; >> break; >> case 0x7d: /* FRSQRTE */ > > Also case 0x7f FRSQRT I think, which will currently fall into > a g_assert_not_reached() for the scalar case. 0x7f FSQRT (vector), yes. I'll fix this case too. r~
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a99f3d0d13..f67360c4c5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10816,6 +10816,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) break; case 0x2f: /* FABS */ case 0x6f: /* FNEG */ + only_in_vector = true; need_fpst = false; break; case 0x7d: /* FRSQRTE */ @@ -10877,9 +10878,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; - case 0x6f: /* FNEG */ - tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); - break; case 0x7d: /* FRSQRTE */ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); break;
These opcodes are only supported as vector operations, not as advsimd scalar. Set only_in_vector, and remove the unreachable implementation of scalar fneg. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/translate-a64.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)