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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71e4834da91sm29697a34.18.2024.12.13.11.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 11:09:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , "Michael S. Tsirkin" , Paolo Bonzini , Peter Maydell , "Edgar E. Iglesias" , Alistair Francis , qemu-ppc@nongnu.org (open list:PReP), qemu-arm@nongnu.org (open list:ARM PrimeCell and...) Subject: [PATCH 25/71] hw/dma: Constify all Property Date: Fri, 13 Dec 2024 13:06:59 -0600 Message-ID: <20241213190750.2513964-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213190750.2513964-1-richard.henderson@linaro.org> References: <20241213190750.2513964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- hw/dma/i82374.c | 2 +- hw/dma/i8257.c | 2 +- hw/dma/pl080.c | 2 +- hw/dma/pl330.c | 2 +- hw/dma/xilinx_axidma.c | 2 +- hw/dma/xlnx-zdma.c | 2 +- hw/dma/xlnx_csu_dma.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c index e72aa2e1ce..032afedde2 100644 --- a/hw/dma/i82374.c +++ b/hw/dma/i82374.c @@ -139,7 +139,7 @@ static void i82374_realize(DeviceState *dev, Error **errp) memset(s->commands, 0, sizeof(s->commands)); } -static Property i82374_properties[] = { +static const Property i82374_properties[] = { DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400), DEFINE_PROP_END_OF_LIST() }; diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 3e6700e53b..8b04177393 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -585,7 +585,7 @@ static void i8257_realize(DeviceState *dev, Error **errp) d->dma_bh = qemu_bh_new(i8257_dma_run, d); } -static Property i8257_properties[] = { +static const Property i8257_properties[] = { DEFINE_PROP_INT32("base", I8257State, base, 0x00), DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index 8e76f88a69..3f392822ed 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -408,7 +408,7 @@ static void pl081_init(Object *obj) s->nchannels = 2; } -static Property pl080_properties[] = { +static const Property pl080_properties[] = { DEFINE_PROP_LINK("downstream", PL080State, downstream, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 0668caed7c..d5a0a1caa2 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1646,7 +1646,7 @@ static void pl330_realize(DeviceState *dev, Error **errp) pl330_fifo_init(&s->fifo, s->data_width / 4 * s->data_buffer_dep); } -static Property pl330_properties[] = { +static const Property pl330_properties[] = { /* CR0 */ DEFINE_PROP_UINT32("num_chnls", PL330State, num_chnls, 8), DEFINE_PROP_UINT8("num_periph_req", PL330State, num_periph_req, 4), diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 73a480bfbf..f09452d0b5 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -611,7 +611,7 @@ static void xilinx_axidma_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -static Property axidma_properties[] = { +static const Property axidma_properties[] = { DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000), DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA, tx_data_dev, TYPE_STREAM_SINK, StreamSink *), diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 46f50631ff..1a63d5f3b2 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -810,7 +810,7 @@ static const VMStateDescription vmstate_zdma = { } }; -static Property zdma_props[] = { +static const Property zdma_props[] = { DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64), DEFINE_PROP_LINK("dma", XlnxZDMA, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 43738c4350..d78dc6444b 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -691,7 +691,7 @@ static const VMStateDescription vmstate_xlnx_csu_dma = { } }; -static Property xlnx_csu_dma_properties[] = { +static const Property xlnx_csu_dma_properties[] = { /* * Ref PG021, Stream Data Width: * Data width in bits of the AXI S2MM AXI4-Stream Data bus.