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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ebb478a497sm3545b6e.10.2024.12.13.11.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 11:13:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Gerd Hoffmann , Mark Cave-Ayland , Joel Stanley , Peter Maydell , Nicholas Piggin , Daniel Henrique Barboza , Harsh Prateek Bora , Alistair Francis , "Edgar E. Iglesias" , qemu-ppc@nongnu.org (open list:New World (mac99)), qemu-arm@nongnu.org (open list:NRF51) Subject: [PATCH 44/71] hw/nvram: Constify all Property Date: Fri, 13 Dec 2024 13:07:18 -0600 Message-ID: <20241213190750.2513964-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213190750.2513964-1-richard.henderson@linaro.org> References: <20241213190750.2513964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- hw/nvram/ds1225y.c | 2 +- hw/nvram/eeprom_at24c.c | 2 +- hw/nvram/fw_cfg.c | 6 +++--- hw/nvram/mac_nvram.c | 2 +- hw/nvram/nrf51_nvm.c | 2 +- hw/nvram/spapr_nvram.c | 2 +- hw/nvram/xlnx-bbram.c | 2 +- hw/nvram/xlnx-efuse.c | 2 +- hw/nvram/xlnx-versal-efuse-cache.c | 2 +- hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +- hw/nvram/xlnx-zynqmp-efuse.c | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c index 6d510dcc68..19bf8d2091 100644 --- a/hw/nvram/ds1225y.c +++ b/hw/nvram/ds1225y.c @@ -142,7 +142,7 @@ static void nvram_sysbus_realize(DeviceState *dev, Error **errp) nvram_post_load(s, 0); } -static Property nvram_sysbus_properties[] = { +static const Property nvram_sysbus_properties[] = { DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000), DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c index ec748e58e7..669920b2b9 100644 --- a/hw/nvram/eeprom_at24c.c +++ b/hw/nvram/eeprom_at24c.c @@ -234,7 +234,7 @@ void at24c_eeprom_reset(DeviceState *state) ee->haveaddr = 0; } -static Property at24c_eeprom_props[] = { +static const Property at24c_eeprom_props[] = { DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0), DEFINE_PROP_UINT8("address-size", EEPROMState, asize, 0), DEFINE_PROP_BOOL("writable", EEPROMState, writable, true), diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index b644577734..fe73a2c1ef 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1103,7 +1103,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data) qemu_register_reset(fw_cfg_machine_reset, s); } -static Property fw_cfg_properties[] = { +static const Property fw_cfg_properties[] = { DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true), DEFINE_PROP_END_OF_LIST(), }; @@ -1294,7 +1294,7 @@ static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) s->entry_order = g_new0(int, fw_cfg_max_entry(s)); } -static Property fw_cfg_io_properties[] = { +static const Property fw_cfg_io_properties[] = { DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, true), DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, @@ -1343,7 +1343,7 @@ static const TypeInfo fw_cfg_io_info = { }; -static Property fw_cfg_mem_properties[] = { +static const Property fw_cfg_mem_properties[] = { DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, true), diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c index e47e52a677..d62ad719c8 100644 --- a/hw/nvram/mac_nvram.c +++ b/hw/nvram/mac_nvram.c @@ -134,7 +134,7 @@ static void macio_nvram_unrealizefn(DeviceState *dev) g_free(s->data); } -static Property macio_nvram_properties[] = { +static const Property macio_nvram_properties[] = { DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0), DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0), DEFINE_PROP_DRIVE("drive", MacIONVRAMState, blk), diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index b1f81752a3..236049462b 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -354,7 +354,7 @@ static void nrf51_nvm_reset(DeviceState *dev) memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); } -static Property nrf51_nvm_properties[] = { +static const Property nrf51_nvm_properties[] = { DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index bfd8aa367e..2251ff2f4c 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -252,7 +252,7 @@ static const VMStateDescription vmstate_spapr_nvram = { }, }; -static Property spapr_nvram_properties[] = { +static const Property spapr_nvram_properties[] = { DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev), DEFINE_PROP_DRIVE("drive", SpaprNvram, blk), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index 1bc58e90ad..4fa528f048 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -520,7 +520,7 @@ static const VMStateDescription vmstate_bbram_ctrl = { } }; -static Property bbram_ctrl_props[] = { +static const Property bbram_ctrl_props[] = { DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *), DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index f7b849f7de..5dae9e8e9a 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -265,7 +265,7 @@ static const PropertyInfo efuse_prop_drive = { .release = efuse_prop_release_drive, }; -static Property efuse_properties[] = { +static const Property efuse_properties[] = { DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *), DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3), DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32), diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c index eaec64d785..1aea27afd3 100644 --- a/hw/nvram/xlnx-versal-efuse-cache.c +++ b/hw/nvram/xlnx-versal-efuse-cache.c @@ -83,7 +83,7 @@ static void efuse_cache_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -static Property efuse_cache_props[] = { +static const Property efuse_cache_props[] = { DEFINE_PROP_LINK("efuse", XlnxVersalEFuseCache, efuse, TYPE_XLNX_EFUSE, XlnxEFuse *), diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c index 8252a5cabe..599aa126fb 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -743,7 +743,7 @@ static const VMStateDescription vmstate_efuse_ctrl = { } }; -static Property efuse_ctrl_props[] = { +static const Property efuse_ctrl_props[] = { DEFINE_PROP_LINK("efuse", XlnxVersalEFuseCtrl, efuse, TYPE_XLNX_EFUSE, XlnxEFuse *), diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index 4e2d1b9d1e..af53187905 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -833,7 +833,7 @@ static const VMStateDescription vmstate_efuse = { } }; -static Property zynqmp_efuse_props[] = { +static const Property zynqmp_efuse_props[] = { DEFINE_PROP_LINK("efuse", XlnxZynqMPEFuse, efuse, TYPE_XLNX_EFUSE, XlnxEFuse *),