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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2a3d2914ac6sm1423214fac.39.2024.12.15.11.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2024 11:06:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 21/67] hw/cpu: Constify all Property Date: Sun, 15 Dec 2024 13:04:47 -0600 Message-ID: <20241215190533.3222854-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241215190533.3222854-1-richard.henderson@linaro.org> References: <20241215190533.3222854-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/cpu/a15mpcore.c | 2 +- hw/cpu/a9mpcore.c | 2 +- hw/cpu/arm11mpcore.c | 2 +- hw/cpu/cluster.c | 2 +- hw/cpu/realview_mpcore.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 967d8d3dd5..5346b8b6c6 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -144,7 +144,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) } } -static Property a15mp_priv_properties[] = { +static const Property a15mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), /* The Cortex-A15MP may have anything from 0 to 224 external interrupt * IRQ lines (with another 32 internal). We default to 128+32, which diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c30ef72c66..c3fdfb92e1 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -158,7 +158,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) } } -static Property a9mp_priv_properties[] = { +static const Property a9mp_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), /* The Cortex-A9MP may have anything from 0 to 224 external interrupt * IRQ lines (with another 32 internal). We default to 64+32, which diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 89c4e35143..193fc182ab 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -131,7 +131,7 @@ static void mpcore_priv_initfn(Object *obj) object_initialize_child(obj, "wdtimer", &s->wdtimer, TYPE_ARM_MPTIMER); } -static Property mpcore_priv_properties[] = { +static const Property mpcore_priv_properties[] = { DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), /* The ARM11 MPCORE TRM says the on-chip controller may have * anything from 0 to 224 external interrupt IRQ lines (with another diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 61289a840d..8e43621b5c 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -25,7 +25,7 @@ #include "hw/qdev-properties.h" #include "qapi/error.h" -static Property cpu_cluster_properties[] = { +static const Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c index 72c792eef1..9a0ff1df86 100644 --- a/hw/cpu/realview_mpcore.c +++ b/hw/cpu/realview_mpcore.c @@ -108,7 +108,7 @@ static void mpcore_rirq_init(Object *obj) } } -static Property mpcore_rirq_properties[] = { +static const Property mpcore_rirq_properties[] = { DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), DEFINE_PROP_END_OF_LIST(), };