Message ID | 20241217062440.884261-2-frank.chang@sifive.com (mailing list archive) |
---|---|
State | New |
Headers | show
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Mon, 16 Dec 2024 22:25:04 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72925e6e8b1sm4354301b3a.139.2024.12.16.22.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2024 22:25:03 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Tommy Wu <tommy.wu@sifive.com>, Frank Chang <frank.chang@sifive.com> Subject: [PATCH v10 1/7] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig Date: Tue, 17 Dec 2024 14:24:34 +0800 Message-Id: <20241217062440.884261-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217062440.884261-1-frank.chang@sifive.com> References: <20241217062440.884261-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; 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Add Smrnmi support
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expand
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diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fe0c4173d2..28b43932db 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -129,6 +129,7 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_smrnmi; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl;