| Message ID | 20241217062440.884261-6-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add Smrnmi support | expand |
Frank, I believe patch 7 should be squashed in with this one. This patch will break 'check-functional' because the 'max' CPU isn't able to support Smrnmi and we're only fixing it 2 patches later. In theory this is fine but it can be problematic when doing bisecting looking for bugs. If you merge patch 7 with this patch please also add: Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Thanks, Daniel On 12/17/24 3:24 AM, frank.chang@sifive.com wrote: > From: Tommy Wu <tommy.wu@sifive.com> > > This adds the properties for ISA extension Smrnmi. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Signed-off-by: Tommy Wu <tommy.wu@sifive.com> > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e6988f44c6..7a4aa235ce 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), > MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e6988f44c6..7a4aa235ce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false),