diff mbox series

[v2,7/9] target/riscv: add shvsatpa

Message ID 20241218114026.1652352-8-dbarboza@ventanamicro.com (mailing list archive)
State New
Headers show
Series target/riscv: add 'sha' support | expand

Commit Message

Daniel Henrique Barboza Dec. 18, 2024, 11:40 a.m. UTC 
shvsatpa is defined in RVA22 as:

"All translation modes supported in satp must be supported in vsatp."

This is always true in TCG so let's claim support for it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c                |   1 +
 tests/data/acpi/riscv64/virt/RHCT | Bin 374 -> 382 bytes
 2 files changed, 1 insertion(+)

diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index 2c7dc6c9ab8d8da9c30ad34294ef28427a4f8f1a..fcd9c95a6ae6e6977e5d9c33a39785269a28aa58 100644
GIT binary patch
delta 47
zcmeyy^pA-v$iq3Lj*)?Z@&80F16CPEMh20I_J^1gOA03b4w&r2sKgP%$iNWC$iM&q
DMU4z8

delta 44
zcmeyz^o@xt$iq3LjFEwX@#91;16C16Mh5PQ_J<~OF?vl7W>n_zVPs$kV`N|e00!3y
Az5oCK
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7aa8a136d6..b5ab97b4de 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -185,6 +185,7 @@  const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
+    ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),