diff mbox series

[v2,8/9] target/riscv: add shgatpa

Message ID 20241218114026.1652352-9-dbarboza@ventanamicro.com (mailing list archive)
State New
Headers show
Series target/riscv: add 'sha' support | expand

Commit Message

Daniel Henrique Barboza Dec. 18, 2024, 11:40 a.m. UTC 
shgatpa is defined in RVA22 as:

"For each supported virtual memory scheme SvNN supported in satp, the
corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare
must also be supported."

Claim support for shgatpa since this is always true for TCG.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c                |   1 +
 tests/data/acpi/riscv64/virt/RHCT | Bin 382 -> 390 bytes
 2 files changed, 1 insertion(+)

diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index fcd9c95a6ae6e6977e5d9c33a39785269a28aa58..695022d56c4ac16607d4c622955ad339fbbfe997 100644
GIT binary patch
delta 45
zcmeyz)W*ye<l!9B#>l|HIAJ1}0jmllBZJID`yH(5i6sSz6TdWZ#4s{2q%kru000jj
B3tRvI

delta 39
vcmZo;{>Q`><l!7r$H>6I_<tgo0jmrnBZJ69`yCVi*K>q0GBCt3GB5xD(EkaU
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b5ab97b4de..41629019e2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -184,6 +184,7 @@  const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+    ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),