diff mbox series

[PULL,23/39] MAINTAINERS: Cover RISC-V HTIF interface

Message ID	20241218223010.1931245-24-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface Date: Thu, 19 Dec 2024 08:29:53 +1000 Message-ID: <20241218223010.1931245-24-alistair.francis@wdc.com> In-Reply-To: <20241218223010.1931245-1-alistair.francis@wdc.com> References: <20241218223010.1931245-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova \| expand [PULL,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova [PULL,02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation [PULL,03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() [PULL,04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS [PULL,05/39] hw/riscv: add riscv-iommu-sys platform device [PULL,06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set [PULL,07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support [PULL,08/39] hw/riscv/riscv-iommu: implement reset protocol [PULL,09/39] docs/specs: add riscv-iommu-sys information [PULL,10/39] target/riscv: Add Tenstorrent Ascalon CPU [PULL,11/39] hw/intc/riscv_aplic: rename is_kvm_aia() [PULL,12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage [PULL,13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() [PULL,14/39] target/riscv/kvm: consider irqchip_split() in aia_create() [PULL,15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers [PULL,16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic [PULL,17/39] target/riscv/kvm: remove irqchip_split() restriction [PULL,18/39] docs: update riscv/virt.rst with kernel-irqchip=split support [PULL,19/39] hw/riscv: Add Microblaze V generic board [PULL,20/39] qtest: allow SPCR acpi table changes [PULL,21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format [PULL,22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V [PULL,23/39] MAINTAINERS: Cover RISC-V HTIF interface [PULL,24/39] hw/char/riscv_htif: Explicit little-endian implementation [PULL,25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses [PULL,26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. [PULL,27/39] hw/riscv: Add a new struct RISCVBootInfo [PULL,28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd [PULL,29/39] target/riscv: Add svukte extension capability variable [PULL,30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled [PULL,31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled [PULL,32/39] target/riscv: Check memory access to meet svukte rule [PULL,33/39] target/riscv: Expose svukte ISA extension [PULL,34/39] target/riscv: Check svukte is not enabled in RV32 [PULL,35/39] target/riscv: Include missing headers in 'vector_internals.h' [PULL,36/39] target/riscv: Include missing headers in 'internals.h' [PULL,37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver [PULL,38/39] target/riscv: add ssstateen [PULL,39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU

Commit Message

Alistair Francis Dec. 18, 2024, 10:29 p.m. UTC

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 27c21cd578..3bba2efbc1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -324,8 +324,10 @@  S: Supported
 F: configs/targets/riscv*
 F: docs/system/target-riscv.rst
 F: target/riscv/
+F: hw/char/riscv_htif.c
 F: hw/riscv/
 F: hw/intc/riscv*
+F: include/hw/char/riscv_htif.h
 F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/