[PULL,v2,11/39] hw/intc/riscv_aplic: rename is_kvm_aia()

Message ID	20241220015441.317236-12-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia() Date: Fri, 20 Dec 2024 11:54:11 +1000 Message-ID: <20241220015441.317236-12-alistair.francis@wdc.com> In-Reply-To: <20241220015441.317236-1-alistair.francis@wdc.com> References: <20241220015441.317236-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova \| expand [PULL,v2,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova [PULL,v2,02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation [PULL,v2,03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() [PULL,v2,04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS [PULL,v2,05/39] hw/riscv: add riscv-iommu-sys platform device [PULL,v2,06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set [PULL,v2,07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support [PULL,v2,08/39] hw/riscv/riscv-iommu: implement reset protocol [PULL,v2,09/39] docs/specs: add riscv-iommu-sys information [PULL,v2,10/39] target/riscv: Add Tenstorrent Ascalon CPU [PULL,v2,11/39] hw/intc/riscv_aplic: rename is_kvm_aia() [PULL,v2,12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage [PULL,v2,13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() [PULL,v2,14/39] target/riscv/kvm: consider irqchip_split() in aia_create() [PULL,v2,15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers [PULL,v2,16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic [PULL,v2,17/39] target/riscv/kvm: remove irqchip_split() restriction [PULL,v2,18/39] docs: update riscv/virt.rst with kernel-irqchip=split support [PULL,v2,19/39] hw/riscv: Add Microblaze V generic board [PULL,v2,20/39] qtest: allow SPCR acpi table changes [PULL,v2,21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format [PULL,v2,22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V [PULL,v2,23/39] MAINTAINERS: Cover RISC-V HTIF interface [PULL,v2,24/39] hw/char/riscv_htif: Explicit little-endian implementation [PULL,v2,25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses [PULL,v2,26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. [PULL,v2,27/39] hw/riscv: Add a new struct RISCVBootInfo [PULL,v2,28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd [PULL,v2,29/39] target/riscv: Add svukte extension capability variable [PULL,v2,30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled [PULL,v2,31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled [PULL,v2,32/39] target/riscv: Check memory access to meet svukte rule [PULL,v2,33/39] target/riscv: Expose svukte ISA extension [PULL,v2,34/39] target/riscv: Check svukte is not enabled in RV32 [PULL,v2,35/39] target/riscv: Include missing headers in 'vector_internals.h' [PULL,v2,36/39] target/riscv: Include missing headers in 'internals.h' [PULL,v2,37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver [PULL,v2,38/39] target/riscv: add ssstateen [PULL,v2,39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU

Message ID

20241220015441.317236-12-alistair.francis@wdc.com (mailing list archive)

State

New

Headers

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia()
Date: Fri, 20 Dec 2024 11:54:11 +1000
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Series

[PULL,v2,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova | expand

Commit Message

Alistair Francis Dec. 20, 2024, 1:54 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.

Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.

Make the helper public because the 'virt' machine will use it as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aplic.h | 1 +
 hw/intc/riscv_aplic.c         | 8 ++++----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index de8532fbc3..fd0e6427d9 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -71,6 +71,7 @@  struct RISCVAPLICState {
 };
 
 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
 
 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 3edab64b97..9f9814a40b 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -154,7 +154,7 @@ 
  * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
  * APLIC Wired.
  */
-static bool is_kvm_aia(bool msimode)
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
 {
     return kvm_irqchip_in_kernel() && msimode;
 }
@@ -857,7 +857,7 @@  static void riscv_aplic_realize(DeviceState *dev, Error **errp)
     uint32_t i;
     RISCVAPLICState *aplic = RISCV_APLIC(dev);
 
-    if (!is_kvm_aia(aplic->msimode)) {
+    if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
         aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
         aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
         aplic->state = g_new0(uint32_t, aplic->num_irqs);
@@ -881,7 +881,7 @@  static void riscv_aplic_realize(DeviceState *dev, Error **errp)
      * have IRQ lines delegated by their parent APLIC.
      */
     if (!aplic->parent) {
-        if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
+        if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
         } else {
             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
@@ -1025,7 +1025,7 @@  DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
 
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
-    if (!is_kvm_aia(msimode)) {
+    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }

[PULL,v2,11/39] hw/intc/riscv_aplic: rename is_kvm_aia()

Commit Message

Patch