diff mbox series

[PULL,v2,33/39] target/riscv: Expose svukte ISA extension

Message ID	20241220015441.317236-34-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, "Fea.Wang" <fea.wang@sifive.com>, Frank Chang <frank.chang@sifive.com>, Jim Shu <jim.shu@sifive.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL v2 33/39] target/riscv: Expose svukte ISA extension Date: Fri, 20 Dec 2024 11:54:33 +1000 Message-ID: <20241220015441.317236-34-alistair.francis@wdc.com> In-Reply-To: <20241220015441.317236-1-alistair.francis@wdc.com> References: <20241220015441.317236-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova \| expand [PULL,v2,01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova [PULL,v2,02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation [PULL,v2,03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() [PULL,v2,04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS [PULL,v2,05/39] hw/riscv: add riscv-iommu-sys platform device [PULL,v2,06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set [PULL,v2,07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support [PULL,v2,08/39] hw/riscv/riscv-iommu: implement reset protocol [PULL,v2,09/39] docs/specs: add riscv-iommu-sys information [PULL,v2,10/39] target/riscv: Add Tenstorrent Ascalon CPU [PULL,v2,11/39] hw/intc/riscv_aplic: rename is_kvm_aia() [PULL,v2,12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage [PULL,v2,13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() [PULL,v2,14/39] target/riscv/kvm: consider irqchip_split() in aia_create() [PULL,v2,15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers [PULL,v2,16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic [PULL,v2,17/39] target/riscv/kvm: remove irqchip_split() restriction [PULL,v2,18/39] docs: update riscv/virt.rst with kernel-irqchip=split support [PULL,v2,19/39] hw/riscv: Add Microblaze V generic board [PULL,v2,20/39] qtest: allow SPCR acpi table changes [PULL,v2,21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format [PULL,v2,22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V [PULL,v2,23/39] MAINTAINERS: Cover RISC-V HTIF interface [PULL,v2,24/39] hw/char/riscv_htif: Explicit little-endian implementation [PULL,v2,25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses [PULL,v2,26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system. [PULL,v2,27/39] hw/riscv: Add a new struct RISCVBootInfo [PULL,v2,28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd [PULL,v2,29/39] target/riscv: Add svukte extension capability variable [PULL,v2,30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled [PULL,v2,31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled [PULL,v2,32/39] target/riscv: Check memory access to meet svukte rule [PULL,v2,33/39] target/riscv: Expose svukte ISA extension [PULL,v2,34/39] target/riscv: Check svukte is not enabled in RV32 [PULL,v2,35/39] target/riscv: Include missing headers in 'vector_internals.h' [PULL,v2,36/39] target/riscv: Include missing headers in 'internals.h' [PULL,v2,37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver [PULL,v2,38/39] target/riscv: add ssstateen [PULL,v2,39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU

Commit Message

Alistair Francis Dec. 20, 2024, 1:54 a.m. UTC

From: "Fea.Wang" <fea.wang@sifive.com>

Add "svukte" in the ISA string when svukte extension is enabled.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 66e00ed260..18f4d94b6e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@  const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
     ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+    ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
     ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
     ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
     ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -1663,6 +1664,7 @@  const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 
 /* These are experimental so mark with 'x-' */
 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+    MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
     DEFINE_PROP_END_OF_LIST(),
 };