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Fri, 20 Dec 2024 08:18:14 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c8acafesm4375189f8f.98.2024.12.20.08.18.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Dec 2024 08:18:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Richard Henderson Subject: [PULL 31/59] accel/tcg: Move TranslationBlock declarations to 'tb-internal.h' Date: Fri, 20 Dec 2024 17:15:22 +0100 Message-ID: <20241220161551.89317-32-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241220161551.89317-1-philmd@linaro.org> References: <20241220161551.89317-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move declarations related to TranslationBlock out of the generic "internal-target.h" to "tb-internal.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20241212185341.2857-11-philmd@linaro.org> --- accel/tcg/internal-target.h | 32 ------------------------------ accel/tcg/tb-internal.h | 39 +++++++++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/translate-all.c | 1 + accel/tcg/translator.c | 1 + 7 files changed, 44 insertions(+), 32 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 0437d798295..1cfa318dc6c 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -36,42 +36,10 @@ static inline void page_table_config_init(void) { } void page_table_config_init(void); #endif -#ifdef CONFIG_USER_ONLY -#include "user/page-protection.h" -/* - * For user-only, page_protect sets the page read-only. - * Since most execution is already on read-only pages, and we'd need to - * account for other TBs on the same page, defer undoing any page protection - * until we receive the write fault. - */ -static inline void tb_lock_page0(tb_page_addr_t p0) -{ - page_protect(p0); -} - -static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1) -{ - page_protect(p1); -} - -static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { } -static inline void tb_unlock_pages(TranslationBlock *tb) { } -#else -void tb_lock_page0(tb_page_addr_t); -void tb_lock_page1(tb_page_addr_t, tb_page_addr_t); -void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t); -void tb_unlock_pages(TranslationBlock *); -#endif - #ifdef CONFIG_SOFTMMU -void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, - unsigned size, - uintptr_t retaddr); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_SOFTMMU */ -bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); - /** * tcg_req_mo: * @type: TCGBar diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 8313f90fd71..90be61f296a 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -9,6 +9,45 @@ #ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H #define ACCEL_TCG_TB_INTERNAL_TARGET_H +#include "exec/cpu-all.h" +#include "exec/exec-all.h" +#include "exec/translation-block.h" + +#ifdef CONFIG_USER_ONLY +#include "user/page-protection.h" +/* + * For user-only, page_protect sets the page read-only. + * Since most execution is already on read-only pages, and we'd need to + * account for other TBs on the same page, defer undoing any page protection + * until we receive the write fault. + */ +static inline void tb_lock_page0(tb_page_addr_t p0) +{ + page_protect(p0); +} + +static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1) +{ + page_protect(p1); +} + +static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { } +static inline void tb_unlock_pages(TranslationBlock *tb) { } +#else +void tb_lock_page0(tb_page_addr_t); +void tb_lock_page1(tb_page_addr_t, tb_page_addr_t); +void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t); +void tb_unlock_pages(TranslationBlock *); +#endif + +#ifdef CONFIG_SOFTMMU +void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, + unsigned size, + uintptr_t retaddr); +#endif /* CONFIG_SOFTMMU */ + +bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); + void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 396fa6f4a6b..e9eaab223f9 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -41,6 +41,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" +#include "tb-internal.h" #include "internal-common.h" #include "internal-target.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 337801feede..b4ccf0cdcb7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "tb-internal.h" #include "trace.h" #include "tb-hash.h" +#include "tb-internal.h" #include "internal-common.h" #include "internal-target.h" #ifdef CONFIG_PLUGIN diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index bdf5a0b7d58..8e272cf790f 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -30,6 +30,7 @@ #include "tcg/tcg.h" #include "tb-hash.h" #include "tb-context.h" +#include "tb-internal.h" #include "internal-common.h" #include "internal-target.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bad3fce0ffb..572a8a87972 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -62,6 +62,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" +#include "tb-internal.h" #include "internal-common.h" #include "internal-target.h" #include "tcg/perf.h" diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index ff5dabc9014..ce5eae4349e 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -19,6 +19,7 @@ #include "tcg/tcg-op-common.h" #include "internal-target.h" #include "disas/disas.h" +#include "tb-internal.h" static void set_can_do_io(DisasContextBase *db, bool val) {