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[189.71.161.74]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9d4474sm37916405ad.142.2024.12.20.21.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 21:46:27 -0800 (PST) From: Davidson Francis To: qemu-devel@nongnu.org Cc: davidsondfgl@gmail.com, Paolo Bonzini , Zhao Liu Subject: [PATCH] target/i386: Improve 16-bit/real mode debug support in GDB Date: Sat, 21 Dec 2024 02:45:49 -0300 Message-Id: <20241221054549.21883-1-davidsondfgl@gmail.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20241219013535.GB4298@darkstar> References: <20241219013535.GB4298@darkstar> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=davidsondfgl@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Debugging 16-bit/real mode code in QEMU+GDB is challenging due to incorrect architecture detection and segmented memory addressing issues. This patch improves the debugging experience by reporting i8086 architecture to GDB when in real mode and converting segmented addresses (CS:EIP, SS:ESP) to their physical equivalents when reporting to GDB. This enables proper instruction disassembly and stack inspection without complex workarounds. Note: Mode switches after GDB attachment still require manual architecture change, as GDB RSP does not support runtime architecture switches. Signed-off-by: Davidson Francis --- target/i386/cpu.c | 8 +++++++- target/i386/gdbstub.c | 15 +++++++++++++-- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5253399459..65bdc48cc0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6404,7 +6404,13 @@ static const gchar *x86_gdb_arch_name(CPUState *cs) #ifdef TARGET_X86_64 return "i386:x86-64"; #else - return "i386"; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + if (env->cr[0] & 1) { + return "i386"; + } else { + return "i8086"; + } #endif } diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 04c49e802d..d600aee953 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -136,7 +136,13 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) return gdb_get_regl(mem_buf, 0); } } else { - return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); + if (n != R_ESP || (env->cr[0] & 1)) { + return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); + } else { + return gdb_get_reg32(mem_buf, + (env->segs[R_SS].selector << 4) + + env->regs[gpr_map32[n]]); + } } } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { int st_index = n - IDX_FP_REGS; @@ -155,7 +161,12 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) } else { switch (n) { case IDX_IP_REG: - return gdb_get_reg(env, mem_buf, env->eip); + if (TARGET_LONG_BITS != 32 || (env->cr[0] & 1)) { + return gdb_get_reg(env, mem_buf, env->eip); + } else { + return gdb_get_reg(env, mem_buf, + (env->segs[R_CS].selector << 4) + env->eip); + } case IDX_FLAGS_REG: return gdb_get_reg32(mem_buf, env->eflags);