diff mbox series

[v3,3/3] hw/loongarch/boot: Support 32bit boot code

Message ID 20241224-la-booting-v3-3-a15bee060a43@flygoat.com (mailing list archive)
State New
Headers show
Series hw/loongarch/booting: Booting protocol refactoring | expand

Commit Message

Jiaxun Yang Dec. 24, 2024, 2:24 p.m. UTC 
Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR
instructions to prevent illegal instructions.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/loongarch/boot.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 9cb13c1f154cb15373d6fdcbcbac883e05472e62..0046ad3e424bdcc488db709945d7059749e0cdc3 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -22,7 +22,7 @@  unsigned memmap_entries;
 ram_addr_t initrd_offset;
 uint64_t initrd_size;
 
-static void generate_secondary_boot_code(void *boot_code)
+static void generate_secondary_boot_code(void *boot_code, bool  is_64bit)
 {
     uint32_t *p = boot_code;
 
@@ -36,7 +36,11 @@  static void generate_secondary_boot_code(void *boot_code)
     /* Clear mailbox. */
     stl_p(p++, 0x1400002d); /* lu12i.w    $t1, 1(0x1)                */
     stl_p(p++, 0x038081ad); /* ori        $t1, $t1, CORE_BUF_20      */
-    stl_p(p++, 0x06481da0); /* iocsrwr.d  $zero, $t1                 */
+    if (is_64bit) {
+        stl_p(p++, 0x06481da0); /* iocsrwr.d  $zero, $t1             */
+    } else {
+        stl_p(p++, 0x064819a0); /* iocsrwr.w  $zero, $t1             */
+    }
 
     /* Enable IPI interrupt. */
     stl_p(p++, 0x1400002c); /* lu12i.w    $t0, 1(0x1)                */
@@ -68,7 +72,11 @@  static void generate_secondary_boot_code(void *boot_code)
     /* Read mail buf and jump to specified entry. */
     stl_p(p++, 0x1400002d); /* lu12i.w    $t1, 1(0x1)                */
     stl_p(p++, 0x038081ad); /* ori        $t1, $t1, CORE_BUF_20      */
-    stl_p(p++, 0x06480dac); /* iocsrrd.d  $t0, $t1                   */
+    if (is_64bit) {
+        stl_p(p++, 0x06480dac); /* iocsrrd.d  $t0, $t1               */
+    } else {
+        stl_p(p++, 0x064809ac); /* iocsrrd.w  $t0, $t1               */
+    }
     stl_p(p++, 0x00150181); /* move       $ra, $t0                   */
     stl_p(p++, 0x4c000020); /* jirl       $zero, $ra, 0              */
 }
@@ -383,7 +391,7 @@  static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
 
     /* Load slave boot code at pflash0 . */
     void *boot_code = g_malloc0(VIRT_FLASH0_SIZE);
-    generate_secondary_boot_code(boot_code);
+    generate_secondary_boot_code(boot_code, is_la64(&lacpu->env));
     rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLASH0_BASE);
 
     CPU_FOREACH(cs) {