| Message ID | 20241230002248.33648-2-deller@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [PULL,1/2] target/hppa: Add CPU reset method | expand |
Hi Helge, On 30/12/24 01:22, deller@kernel.org wrote: > From: Helge Deller <deller@gmx.de> > > Add the CPU reset method, which resets all CPU registers and the TLB to > zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and > start execution at address 0xf0000004. > Although we currently want to zero out all values in the CPUHPPAState > struct, add the end_reset_fields marker in case the state structs gets > extended with other variables later on which should not be reset. This patch is doing multiple things at once. > Signed-off-by: Helge Deller <deller@gmx.de> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > hw/hppa/machine.c | 6 +++--- > target/hppa/cpu.c | 26 ++++++++++++++++++++++++-- > target/hppa/cpu.h | 5 +++++ > 3 files changed, 32 insertions(+), 5 deletions(-) > diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c > index c38439c180..cb1b5191a4 100644 > --- a/target/hppa/cpu.c > +++ b/target/hppa/cpu.c > @@ -194,11 +194,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) > > static void hppa_cpu_initfn(Object *obj) > { > - CPUState *cs = CPU(obj); > HPPACPU *cpu = HPPA_CPU(obj); > CPUHPPAState *env = &cpu->env; > > - cs->exception_index = -1; > cpu_hppa_loaded_fr0(env); > cpu_hppa_put_psw(env, PSW_W); This is reset code. Should PSW_M bit set on hard reset? > } > @@ -235,15 +233,39 @@ static const TCGCPUOps hppa_tcg_ops = { > #endif /* !CONFIG_USER_ONLY */ > }; > > +static void hppa_cpu_reset_hold(Object *obj, ResetType type) > +{ > + HPPACPU *cpu = HPPA_CPU(obj); > + HPPACPUClass *scc = HPPA_CPU_GET_CLASS(cpu); > + CPUHPPAState *env = &cpu->env; > + CPUState *cs = CPU(cpu); > + > + if (scc->parent_phases.hold) { > + scc->parent_phases.hold(obj, type); > + } > + > + memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); > + cpu_set_pc(cs, 0xf0000004); > + cpu_hppa_put_psw(env, hppa_is_pa20(env) ? PSW_W : 0); PSW_W is already cleared in cpu_hppa_put_psw() for PA1.x. > + cpu_hppa_loaded_fr0(env); > + > + cs->exception_index = -1; > + cs->halted = 0; > +} For clarity I'll respin your patch including my comments.
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index a31dc32a9f..05fd43ce9c 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -655,12 +655,12 @@ static void hppa_machine_reset(MachineState *ms, ResetType type) for (i = 0; i < smp_cpus; i++) { CPUState *cs = CPU(cpu[i]); + /* reset CPU */ + resettable_reset(OBJECT(cs), RESET_TYPE_COLD); + cpu_set_pc(cs, firmware_entry); cpu[i]->env.psw = PSW_Q; cpu[i]->env.gr[5] = CPU_HPA + i * 0x1000; - - cs->exception_index = -1; - cs->halted = 0; } /* already initialized by machine_hppa_init()? */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c180..cb1b5191a4 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -194,11 +194,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) static void hppa_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); HPPACPU *cpu = HPPA_CPU(obj); CPUHPPAState *env = &cpu->env; - cs->exception_index = -1; cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); } @@ -235,15 +233,39 @@ static const TCGCPUOps hppa_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; +static void hppa_cpu_reset_hold(Object *obj, ResetType type) +{ + HPPACPU *cpu = HPPA_CPU(obj); + HPPACPUClass *scc = HPPA_CPU_GET_CLASS(cpu); + CPUHPPAState *env = &cpu->env; + CPUState *cs = CPU(cpu); + + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj, type); + } + + memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); + cpu_set_pc(cs, 0xf0000004); + cpu_hppa_put_psw(env, hppa_is_pa20(env) ? PSW_W : 0); + cpu_hppa_loaded_fr0(env); + + cs->exception_index = -1; + cs->halted = 0; +} + static void hppa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); HPPACPUClass *acc = HPPA_CPU_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, hppa_cpu_realizefn, &acc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL, + &acc->parent_phases); + cc->class_by_name = hppa_cpu_class_by_name; cc->has_work = hppa_cpu_has_work; cc->mmu_index = hppa_cpu_mmu_index; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index e45ba50a59..32a674a8b8 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -263,6 +263,9 @@ typedef struct CPUArchState { IntervalTreeRoot tlb_root; HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; } CPUHPPAState; /** @@ -281,6 +284,7 @@ struct ArchCPU { /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. * * An HPPA CPU model. */ @@ -288,6 +292,7 @@ struct HPPACPUClass { CPUClass parent_class; DeviceRealize parent_realize; + ResettablePhases parent_phases; }; #include "exec/cpu-all.h"