Message ID | 20250102180654.1420056-15-richard.henderson@linaro.org (mailing list archive) |
---|---|
State | New |
Headers | show
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([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72ad3393d5fsm20604456b3a.154.2025.01.02.10.07.06 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:07:06 -0800 (PST) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 14/73] target/i386: Use tcg_op_supported Date: Thu, 2 Jan 2025 10:05:54 -0800 Message-ID: <20250102180654.1420056-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102180654.1420056-1-richard.henderson@linaro.org> References: <20250102180654.1420056-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
tcg: Merge *_i32 and *_i64 opcodes
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expand
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On 2/1/25 19:05, Richard Henderson wrote: > Do not reference TCG_TARGET_HAS_* directly. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/tcg/emit.c.inc | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index a2b940a5c3..00f7a6123a 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -24,9 +24,9 @@ * The exact opcode to check depends on 32- vs. 64-bit. */ #ifdef TARGET_X86_64 -#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i64 +#define INDEX_op_extract2_tl INDEX_op_extract2_i64 #else -#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i32 +#define INDEX_op_extract2_tl INDEX_op_extract2_i32 #endif #define MMX_OFFSET(reg) \ @@ -2993,7 +2993,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode) tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); while (vec_len > 8) { vec_len -= 8; - if (TCG_TARGET_HAS_extract2_tl) { + if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL)) { /* * Load the next byte of the result into the high byte of T. * TCG does a similar expansion of deposit to shl+extract2; by
Do not reference TCG_TARGET_HAS_* directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/i386/tcg/emit.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)