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([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9f68e4sm230148315ad.211.2025.01.02.10.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:16:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, Alistair.Francis@wdc.com Subject: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Date: Thu, 2 Jan 2025 10:16:01 -0800 Message-ID: <20250102181601.1421059-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250102181601.1421059-1-richard.henderson@linaro.org> References: <20250102181601.1421059-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Acked-by: Alistair Francis --- tcg/riscv/tcg-target-has.h | 8 +++++++- tcg/riscv/tcg-target.c.inc | 13 +++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index 10e61edc45..ea38ee5cbb 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ return ofs || (cpuinfo & CPUINFO_ZBA); } - return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; + switch (len) { + case 1: + return (cpuinfo & CPUINFO_ZBS) && ofs != 0; + case 16: + return (cpuinfo & CPUINFO_ZBB) && ofs == 0; + } + return false; } #define TCG_TARGET_extract_valid tcg_target_extract_valid diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 12c3cffcc0..83ec7cd980 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -162,6 +162,7 @@ typedef enum { OPC_ANDI = 0x7013, OPC_AUIPC = 0x17, OPC_BEQ = 0x63, + OPC_BEXTI = 0x48005013, OPC_BGE = 0x5063, OPC_BGEU = 0x7063, OPC_BLT = 0x4063, @@ -2307,9 +2308,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, } else { tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); } - } else if (a2 == 0 && args[3] == 16) { + break; + } + switch (args[3]) { + case 1: + tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2); + break; + case 16: + tcg_debug_assert(a2 == 0); tcg_out_ext16u(s, a0, a1); - } else { + break; + default: g_assert_not_reached(); } break;