Message ID | 20250103171037.11265-4-philmd@linaro.org (mailing list archive) |
---|---|
State | New |
Headers | show
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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219578sm493380585e9.20.2025.01.03.09.10.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Jan 2025 09:10:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: Pierrick Bouvier <pierrick.bouvier@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Kito Cheng <kito.cheng@sifive.com>, Richard Henderson <richard.henderson@linaro.org>, Keith Packard <keithp@keithp.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= <alex.bennee@linaro.org>, Thomas Huth <thuth@redhat.com>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PATCH 3/5] semihosting/arm-compat: Include missing 'cpu.h' header Date: Fri, 3 Jan 2025 18:10:35 +0100 Message-ID: <20250103171037.11265-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250103171037.11265-1-philmd@linaro.org> References: <20250103171037.11265-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
semihosting: Reduce target specific code
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expand
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diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index d78c6428b90..86e5260e504 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -166,6 +166,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs) #endif +#include "cpu.h" #include "common-semi-target.h" /*
ARM semihosting implementations in "common-semi-target.h" must de-reference the target CPUArchState, which is declared in each target "cpu.h" header. Include it in order to avoid when refactoring: In file included from ../../semihosting/arm-compat-semi.c:169: ../target/riscv/common-semi-target.h:16:5: error: use of undeclared identifier 'RISCVCPU' 16 | RISCVCPU *cpu = RISCV_CPU(cs); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- semihosting/arm-compat-semi.c | 1 + 1 file changed, 1 insertion(+)