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Mon, 06 Jan 2025 09:37:46 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([189.110.107.205]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f4478ac7dbsm34139317a91.50.2025.01.06.09.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2025 09:37:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 2/2] target/riscv: add trace in riscv_raise_exception() Date: Mon, 6 Jan 2025 14:37:34 -0300 Message-ID: <20250106173734.412353-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250106173734.412353-1-dbarboza@ventanamicro.com> References: <20250106173734.412353-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When using system mode we can get the CPU traps being taken via the 'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of logging/showing exceptions to users. Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users to check all exceptions being thrown. This is particularly useful to help identifying insns that are throwing SIGILLs. As it is today we need to debug their binaries to identify where the illegal insns are: $ ~/work/qemu/build/qemu-riscv64 -cpu rv64 ./foo.out Illegal instruction (core dumped) After this change users can capture the trace and use EPC to pinpoint the insn: $ ~/work/qemu/build/qemu-riscv64 -cpu rv64 -trace riscv_exception ./foo.out riscv_exception 8 (user_ecall) on epc 0x17cd2 riscv_exception 8 (user_ecall) on epc 0x17cda riscv_exception 8 (user_ecall) on epc 0x17622 (...) riscv_exception 2 (illegal_instruction) on epc 0x1053a Illegal instruction (core dumped) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 6 ++++++ target/riscv/trace-events | 3 +++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 29c104bc23..29de8eb43d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "trace.h" /* Exceptions processing helpers */ G_NORETURN void riscv_raise_exception(CPURISCVState *env, @@ -31,6 +32,11 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, uintptr_t pc) { CPUState *cs = env_cpu(env); + + trace_riscv_exception(exception, + riscv_cpu_get_trap_name(exception, false), + env->pc); + cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 49ec4d3b7d..93837f82a1 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -9,3 +9,6 @@ pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64 + +# op_helper.c +riscv_exception(uint32_t exception, const char *desc, uint64_t epc) "%u (%s) on epc 0x%"PRIx64""