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Fri, 10 Jan 2025 00:21:48 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f22ee09sm9278715ad.200.2025.01.10.00.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2025 00:21:48 -0800 (PST) From: Atish Patra Date: Fri, 10 Jan 2025 00:21:29 -0800 Subject: [PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension MIME-Version: 1.0 Message-Id: <20250110-counter_delegation-v5-1-e83d797ae294@rivosinc.com> References: <20250110-counter_delegation-v5-0-e83d797ae294@rivosinc.com> In-Reply-To: <20250110-counter_delegation-v5-0-e83d797ae294@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: kaiwenxue1@gmail.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com, Kaiwen Xue X-Mailer: b4 0.15-dev-13183 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dace670e5e0f..4f5772ae5b60 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -192,6 +192,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), @@ -201,6 +202,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ee7c90871047..4fe2144ec713 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -79,6 +79,8 @@ struct RISCVCPUConfig { bool ext_smstateen; bool ext_sstc; bool ext_smcntrpmf; + bool ext_smcsrind; + bool ext_sscsrind; bool ext_svadu; bool ext_svinval; bool ext_svnapot;