| Message ID | 20250111130653.1239737-1-baturo.alexey@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Support Supm and Sspm as part of Zjpm v1.0 | expand |
Hi Alexey, On 1/11/25 10:06 AM, baturo.alexey@gmail.com wrote: > From: Alexey Baturo <baturo.alexey@gmail.com> > > The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are used in profile specification. > Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only Smnpm. > > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> > --- This doesn't apply in the current alistair/riscv-to-apply.next tree. It's a trivial rebase, so if you could rebase it and send it again that would be great. I fixed the conflicts and tested it with the RVA23 patches I have, and it works. So please also add a Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Thanks, Daniel > target/riscv/cpu.c | 23 +++++++++++++++++++++++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 25 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index dace670e5e..8c5801b87a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -202,10 +202,12 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), > + ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), > ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), > + ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm), > ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > @@ -1612,6 +1614,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), > MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), > MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), > + MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false), > + MULTI_EXT_CFG_BOOL("supm", ext_supm, false), > > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > @@ -2756,6 +2760,24 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { > }, > }; > > +static RISCVCPUImpliedExtsRule SUPM_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_supm), > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_ssnpm), CPU_CFG_OFFSET(ext_smnpm), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > +static RISCVCPUImpliedExtsRule SSPM_IMPLIED = { > + .ext = CPU_CFG_OFFSET(ext_sspm), > + .implied_multi_exts = { > + CPU_CFG_OFFSET(ext_smnpm), > + > + RISCV_IMPLIED_EXTS_RULE_END > + }, > +}; > + > RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { > &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, > &RVM_IMPLIED, &RVV_IMPLIED, NULL > @@ -2774,6 +2796,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { > &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, > + &SUPM_IMPLIED, &SSPM_IMPLIED, > NULL > }; > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index ee7c908710..76579b9b95 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -133,6 +133,8 @@ struct RISCVCPUConfig { > bool ext_ssnpm; > bool ext_smnpm; > bool ext_smmpm; > + bool ext_sspm; > + bool ext_supm; > bool rvv_ta_all_1s; > bool rvv_ma_all_1s; > bool rvv_vl_half_avl;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dace670e5e..8c5801b87a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -202,10 +202,12 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm), ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1612,6 +1614,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), + MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false), + MULTI_EXT_CFG_BOOL("supm", ext_supm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), @@ -2756,6 +2760,24 @@ static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = { }, }; +static RISCVCPUImpliedExtsRule SUPM_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_supm), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_ssnpm), CPU_CFG_OFFSET(ext_smnpm), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule SSPM_IMPLIED = { + .ext = CPU_CFG_OFFSET(ext_sspm), + .implied_multi_exts = { + CPU_CFG_OFFSET(ext_smnpm), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL @@ -2774,6 +2796,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, + &SUPM_IMPLIED, &SSPM_IMPLIED, NULL }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ee7c908710..76579b9b95 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -133,6 +133,8 @@ struct RISCVCPUConfig { bool ext_ssnpm; bool ext_smnpm; bool ext_smmpm; + bool ext_sspm; + bool ext_supm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl;