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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d0casm10891447f8f.11.2025.01.12.16.47.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 12 Jan 2025 16:47:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Paul Burton , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 01/23] hw/mips/cps: Keep reference of vCPUs in MIPSCPSState Date: Mon, 13 Jan 2025 01:47:26 +0100 Message-ID: <20250113004748.41658-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113004748.41658-1-philmd@linaro.org> References: <20250113004748.41658-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When a QOM object create children with object_new(), it is better to keep reference to them for further use. In particular, this allow to remove one global &first_cpu use. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cps.h | 1 + hw/mips/cps.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 05ef9f76b74..0968b57c5a0 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -40,6 +40,7 @@ struct MIPSCPSState { char *cpu_type; bool cpu_is_bigendian; + MIPSCPU **cpus; MemoryRegion container; MIPSGCRState gcr; MIPSGICState gic; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 293b405b965..494213b2ab6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -73,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) return; } + s->cpus = g_new(MIPSCPU *, s->num_vp); for (int i = 0; i < s->num_vp; i++) { MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); CPUMIPSState *env = &cpu->env; @@ -91,6 +92,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { return; } + s->cpus[i] = cpu; /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -146,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ - gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; + gcr_base = s->cpus[0]->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,