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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4b81a4sm13245516f8f.68.2025.01.13.11.56.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 10/19] hw/mips/bootloader: Propagate CPU to bl_gen_write_u[32, 64, long]() Date: Mon, 13 Jan 2025 20:55:16 +0100 Message-ID: <20250113195525.57150-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target agnostic CPU pointer to the publicly declared bl_gen_write_u32(), bl_gen_write_u64() and bl_gen_write_ulong() functions. For the Malta machine in bl_setup_gt64120_jump_kernel(), pass its first CPU (the one we want to start running the bootloader). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 13 ++++++++++--- hw/mips/bootloader.c | 9 ++++++--- hw/mips/boston.c | 6 +++--- hw/mips/malta.c | 19 ++++++++++--------- 4 files changed, 29 insertions(+), 18 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 8533a16ca62..bc54ea8c7fb 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,6 +10,7 @@ #define HW_MIPS_BOOTLOADER_H #include "exec/cpu-defs.h" +#include "target/mips/cpu-qom.h" /** * bl_gen_jump_to: Generate bootloader code to jump to an address @@ -47,30 +48,36 @@ void bl_gen_jump_kernel(void **ptr, * bl_gen_write_ulong: Generate bootloader code to write an unsigned long * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); +void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr, + target_ulong addr, target_ulong val); /** * bl_gen_write_u32: Generate bootloader code to write a 32-bit unsigned * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); +void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint32_t val); /** * bl_gen_write_u64: Generate bootloader code to write a 64-bit unsigned * value at an address * + * @cpu: The MIPS CPU which will run the bootloader code * @ptr: Pointer to buffer where to write the bootloader code * @addr: Address to write to * @val: Value to write at @addr */ -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef20968..7db3bf7511f 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -277,7 +277,8 @@ void bl_gen_jump_kernel(void **p, bl_gen_jump_to(p, kernel_addr); } -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, + target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); @@ -288,14 +289,16 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const MIPSCPU *cpu, void **p, + target_ulong addr, uint32_t val) { bl_gen_li(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const MIPSCPU *cpu, void **p, + target_ulong addr, uint64_t val) { bl_gen_dli(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 491e1c4f7ea..b646c104df7 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -330,19 +330,19 @@ static void gen_firmware(const MIPSCPU *cpu, void *p, /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_u64(&p, regaddr, + bl_gen_write_u64(cpu, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f7eb990c629..9bc3fc9da3e 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -627,6 +627,7 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; + const MIPSCPU *cpu = s->cpus[0]; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN @@ -638,29 +639,29 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(cpu, p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(cpu, p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -671,12 +672,12 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg)));