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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e3840bfsm13212260f8f.39.2025.01.13.11.56.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 11:56:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 14/19] hw/mips/bootloader: Propagate CPU env to bl_gen_s[w, d]() Date: Mon, 13 Jan 2025 20:55:20 +0100 Message-ID: <20250113195525.57150-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250113195525.57150-1-philmd@linaro.org> References: <20250113195525.57150-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Propagate the target specific CPU env to the locally declared bl_gen_sw() and bl_gen_sd() functions. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 464ed5f4f1a..288dccce473 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -194,7 +194,8 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) st_nm32_p(ptr, insn); } -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { bl_gen_sw_nm(p, rt, base, offset); @@ -203,7 +204,8 @@ static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) } } -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const CPUMIPSState *env, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { bl_gen_i_type(p, 0x3f, base, rt, offset); @@ -292,9 +294,9 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p, bl_gen_load_ulong(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0); } } @@ -305,7 +307,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p, bl_gen_li(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0); } void bl_gen_write_u64(const MIPSCPU *cpu, void **p, @@ -315,5 +317,5 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p, bl_gen_dli(env, p, BL_REG_K0, val); bl_gen_load_ulong(env, p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0); }