| Message ID | 20250114132012.1224941-4-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: RVA23 profile support | expand |
On Tue, Jan 14, 2025 at 10:20:11AM -0300, Daniel Henrique Barboza wrote: > Add RVA23U64 as described in [1]. This profile does not share all > mandatory RVA22U64 extensions so we can't use RVA22U64 as a parent. We > need to declare all mandatory extensions from scratch. But it does share all mandatory extensions of rva22u64 and you do use it as a parent :-) Thanks, drew > > A new "rva23u64" CPU is also added. > > [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 35 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index d56b067bf2..53ead481a9 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -40,6 +40,7 @@ > #define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") > #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") > #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") > +#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8d0563527f..e10ecc4ece 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2394,9 +2394,35 @@ static RISCVCPUProfile RVA22S64 = { > } > }; > > +/* > + * All mandatory extensions from RVA22U64 are present > + * in RVA23U64 so set RVA22 as a parent. We need to > + * declare just the newly added mandatory extensions. > + */ > +static RISCVCPUProfile RVA23U64 = { > + .parent = &RVA22U64, > + .name = "rva23u64", > + .misa_ext = RVV, > + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, > + .satp_mode = RISCV_PROFILE_ATTR_UNUSED, > + .ext_offsets = { > + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb), > + CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl), > + CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop), > + CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb), > + CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs), > + > + /* mandatory named features for this profile */ > + CPU_CFG_OFFSET(ext_supm), > + > + RISCV_PROFILE_EXT_LIST_END > + } > +}; > + > RISCVCPUProfile *riscv_profiles[] = { > &RVA22U64, > &RVA22S64, > + &RVA23U64, > NULL, > }; > > @@ -2883,6 +2909,13 @@ static void rva22s64_profile_cpu_init(Object *obj) > > RVA22S64.enabled = true; > } > + > +static void rva23u64_profile_cpu_init(Object *obj) > +{ > + rv64i_bare_cpu_init(obj); > + > + RVA23U64.enabled = true; > +} > #endif > > static const gchar *riscv_gdb_arch_name(CPUState *cs) > @@ -3162,6 +3195,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), > + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init), > #endif /* TARGET_RISCV64 */ > }; > > -- > 2.47.1 > >
On 1/14/25 11:57 AM, Andrew Jones wrote: > On Tue, Jan 14, 2025 at 10:20:11AM -0300, Daniel Henrique Barboza wrote: >> Add RVA23U64 as described in [1]. This profile does not share all >> mandatory RVA22U64 extensions so we can't use RVA22U64 as a parent. We >> need to declare all mandatory extensions from scratch. > > But it does share all mandatory extensions of rva22u64 and you do use it > as a parent :-) Oooops. Forgot to update the commit msg :D Daniel > > Thanks, > drew > >> >> A new "rva23u64" CPU is also added. >> >> [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> target/riscv/cpu-qom.h | 1 + >> target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ >> 2 files changed, 35 insertions(+) >> >> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h >> index d56b067bf2..53ead481a9 100644 >> --- a/target/riscv/cpu-qom.h >> +++ b/target/riscv/cpu-qom.h >> @@ -40,6 +40,7 @@ >> #define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") >> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") >> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") >> +#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") >> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") >> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") >> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 8d0563527f..e10ecc4ece 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -2394,9 +2394,35 @@ static RISCVCPUProfile RVA22S64 = { >> } >> }; >> >> +/* >> + * All mandatory extensions from RVA22U64 are present >> + * in RVA23U64 so set RVA22 as a parent. We need to >> + * declare just the newly added mandatory extensions. >> + */ >> +static RISCVCPUProfile RVA23U64 = { >> + .parent = &RVA22U64, >> + .name = "rva23u64", >> + .misa_ext = RVV, >> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, >> + .satp_mode = RISCV_PROFILE_ATTR_UNUSED, >> + .ext_offsets = { >> + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb), >> + CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl), >> + CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop), >> + CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb), >> + CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs), >> + >> + /* mandatory named features for this profile */ >> + CPU_CFG_OFFSET(ext_supm), >> + >> + RISCV_PROFILE_EXT_LIST_END >> + } >> +}; >> + >> RISCVCPUProfile *riscv_profiles[] = { >> &RVA22U64, >> &RVA22S64, >> + &RVA23U64, >> NULL, >> }; >> >> @@ -2883,6 +2909,13 @@ static void rva22s64_profile_cpu_init(Object *obj) >> >> RVA22S64.enabled = true; >> } >> + >> +static void rva23u64_profile_cpu_init(Object *obj) >> +{ >> + rv64i_bare_cpu_init(obj); >> + >> + RVA23U64.enabled = true; >> +} >> #endif >> >> static const gchar *riscv_gdb_arch_name(CPUState *cs) >> @@ -3162,6 +3195,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { >> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), >> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), >> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), >> + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init), >> #endif /* TARGET_RISCV64 */ >> }; >> >> -- >> 2.47.1 >> >>
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index d56b067bf2..53ead481a9 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -40,6 +40,7 @@ #define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") +#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d0563527f..e10ecc4ece 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2394,9 +2394,35 @@ static RISCVCPUProfile RVA22S64 = { } }; +/* + * All mandatory extensions from RVA22U64 are present + * in RVA23U64 so set RVA22 as a parent. We need to + * declare just the newly added mandatory extensions. + */ +static RISCVCPUProfile RVA23U64 = { + .parent = &RVA22U64, + .name = "rva23u64", + .misa_ext = RVV, + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, + .satp_mode = RISCV_PROFILE_ATTR_UNUSED, + .ext_offsets = { + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb), + CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl), + CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop), + CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb), + CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(ext_supm), + + RISCV_PROFILE_EXT_LIST_END + } +}; + RISCVCPUProfile *riscv_profiles[] = { &RVA22U64, &RVA22S64, + &RVA23U64, NULL, }; @@ -2883,6 +2909,13 @@ static void rva22s64_profile_cpu_init(Object *obj) RVA22S64.enabled = true; } + +static void rva23u64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA23U64.enabled = true; +} #endif static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -3162,6 +3195,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init), #endif /* TARGET_RISCV64 */ };
Add RVA23U64 as described in [1]. This profile does not share all mandatory RVA22U64 extensions so we can't use RVA22U64 as a parent. We need to declare all mandatory extensions from scratch. A new "rva23u64" CPU is also added. [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)