@@ -9,6 +9,10 @@
(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
(uint64_t)(mask)))
+#ifndef GENMASK_ULL
+#define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
+#endif
+
/* Extension context status mask */
#define EXT_STATUS_MASK 0x3ULL
@@ -933,9 +937,8 @@ typedef enum RISCVException {
MHPMEVENTH_BIT_VSINH | \
MHPMEVENTH_BIT_VUINH)
-#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
-#define MHPMEVENT_IDX_MASK 0xFFFFF
-#define MHPMEVENT_SSCOF_RESVD 16
+#define MHPMEVENT_SSCOF_MASK GENMASK_ULL(63, 56)
+#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK)
/* RISC-V-specific interrupt pending bits. */
#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
As per the latest privilege specification v1.13[1], the sscofpmf only reserves first 8 bits of hpmeventX. Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu_bits.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)