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Fri, 17 Jan 2025 05:43:09 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384c75283sm173209666b.8.2025.01.17.05.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 05:43:07 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id F114660858; Fri, 17 Jan 2025 13:42:58 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Pierrick Bouvier , Julian Ganz , Richard Henderson , Paolo Bonzini Subject: [PULL 22/37] accel/tcg: also suppress asynchronous IRQs for cpu_io_recompile Date: Fri, 17 Jan 2025 13:42:41 +0000 Message-Id: <20250117134256.2079356-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250117134256.2079356-1-alex.bennee@linaro.org> References: <20250117134256.2079356-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While it would be technically correct to allow an IRQ to happen (as the offending instruction never really completed) it messes up instrumentation. We already take care to only use memory instrumentation on the block, we should also suppress IRQs. Reviewed-by: Pierrick Bouvier Reviewed-by: Julian Ganz Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20250116160306.1709518-23-alex.bennee@linaro.org> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 453eb20ec9..d56ca13cdd 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -633,9 +633,10 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * Exit the loop and potentially generate a new TB executing the * just the I/O insns. We also limit instrumentation to memory * operations only (which execute after completion) so we don't - * double instrument the instruction. + * double instrument the instruction. Also don't let an IRQ sneak + * in before we execute it. */ - cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n; + cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_NOIRQ | n; if (qemu_loglevel_mask(CPU_LOG_EXEC)) { vaddr pc = cpu->cc->get_pc(cpu);