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[124.169.212.233]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2cea0b91sm18249435ad.49.2025.01.17.09.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:03:19 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Dmitry Fleytman , Akihiko Odaki , Jason Wang , Sriram Yagnaraman , Fabiano Rosas , Laurent Vivier , Paolo Bonzini Subject: [PATCH 1/9] qtest/e1000e|igb: Clear interrupt-cause and msix pending bits after irq Date: Sat, 18 Jan 2025 03:02:57 +1000 Message-ID: <20250117170306.403075-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117170306.403075-1-npiggin@gmail.com> References: <20250117170306.403075-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The e1000e and igb tests do not clear the ICR/EICR cause bits (or set auto-clear) on seeing queue interrupts, which inhibits the triggering of a new interrupt. The msix pending bit which is used to test for the interrupt is also not cleared (the vector is masked). Fix this by clearing the ICR/EICR cause bits, and the msix pending bit using the PBACLR device register. Signed-off-by: Nicholas Piggin --- tests/qtest/e1000e-test.c | 9 ++++++++- tests/qtest/igb-test.c | 8 ++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c index de9738fdb74..746d26cfb67 100644 --- a/tests/qtest/e1000e-test.c +++ b/tests/qtest/e1000e-test.c @@ -66,6 +66,10 @@ static void e1000e_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *a /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read ICR to make it ready for next interrupt, assert TXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_TXQ0); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_TX0_MSG_ID)); /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, ==, @@ -117,7 +121,10 @@ static void e1000e_receive_verify(QE1000E *d, int *test_sockets, QGuestAllocator /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); - + /* Read ICR to make it ready for next interrupt, assert RXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_RXQ0); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_RX0_MSG_ID)); /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) & E1000_RXD_STAT_DD, ==, E1000_RXD_STAT_DD); diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c index 3d397ea6973..cf8b4131cf2 100644 --- a/tests/qtest/igb-test.c +++ b/tests/qtest/igb-test.c @@ -69,6 +69,10 @@ static void igb_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *allo /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_TX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert TXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_TX0_MSG_ID)); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_TX0_MSG_ID)); /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, ==, @@ -120,6 +124,10 @@ static void igb_receive_verify(QE1000E *d, int *test_sockets, QGuestAllocator *a /* Wait for TX WB interrupt */ e1000e_wait_isr(d, E1000E_RX0_MSG_ID); + /* Read EICR which clears it ready for next interrupt, assert RXQ0 cause */ + g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_RX0_MSG_ID)); + /* Write PBACLR to clear the MSIX pending bit */ + e1000e_macreg_write(d, E1000_PBACLR, (1 << E1000E_RX0_MSG_ID)); /* Check DD bit */ g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &