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[124.169.212.233]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2cea0b91sm18249435ad.49.2025.01.17.09.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:03:37 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Dmitry Fleytman , Akihiko Odaki , Jason Wang , Sriram Yagnaraman , Fabiano Rosas , Laurent Vivier , Paolo Bonzini Subject: [PATCH 5/9] net/igb: Fix EITR LLI and counter fields Date: Sat, 18 Jan 2025 03:03:01 +1000 Message-ID: <20250117170306.403075-6-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117170306.403075-1-npiggin@gmail.com> References: <20250117170306.403075-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IGB EITR registers have counter fields which reflect the current ITR and LLI counter values, as well as a bit to enable LLI moderation, and a bit to write the register without modifying the counter fields. Implement the ITR counter and log an unimp message if software tries to enable LLI moderation. Fix the implementation of the counter ignore bit. Signed-off-by: Nicholas Piggin --- hw/net/igb_regs.h | 8 +++++-- hw/net/igb_core.c | 53 ++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 51 insertions(+), 10 deletions(-) diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 1ed5ee5039a..b612248264a 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -321,8 +321,12 @@ union e1000_adv_rx_desc { #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ -/* Extended Interrupt Cause Set */ -/* E1000_EITR_CNT_IGNR is only for 82576 and newer */ +/* Extended Interrupt Throttle */ +/* These are only for 82576 and newer */ +#define E1000_EITR_INTERVAL 0x00007FFC +#define E1000_EITR_LLI_EN 0x00008000 +#define E1000_EITR_LLI_CNT 0x001F0000 +#define E1000_EITR_ITR_CNT 0x7FE00000 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 94f9785749a..cdebc917d2e 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -140,12 +140,8 @@ static void igb_msix_notify(IGBCore *core, unsigned int cause) } static inline void -igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) +igb_intrmgr_arm_timer(IGBIntrDelayTimer *timer, int64_t delay_ns) { - int64_t delay_ns = - (int64_t)((timer->core->mac[timer->delay_reg] & 0x7FFC) >> 2) * - timer->delay_resolution_ns; - trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); @@ -153,6 +149,16 @@ igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) timer->running = true; } +static inline void +igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) +{ + uint32_t interval = (timer->core->mac[timer->delay_reg] & + E1000_EITR_INTERVAL) >> 2; + int64_t delay_ns = (int64_t)interval * timer->delay_resolution_ns; + + igb_intrmgr_arm_timer(timer, delay_ns); +} + static void igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) { @@ -2881,7 +2887,22 @@ igb_mac_swsm_read(IGBCore *core, int index) static uint32_t igb_mac_eitr_read(IGBCore *core, int index) { - return core->eitr_guest_value[index - EITR0]; + uint32_t eitr_num = index - EITR0; + uint32_t val = core->mac[eitr_num]; + IGBIntrDelayTimer *timer = &core->eitr[eitr_num]; + + if (timer->running) { /* ITR is enabled, get ITR counter */ + int64_t remains = timer_expire_time_ns(timer->timer) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + if (remains > 0) { + /* CNT is the most significant 10 of 12 bits */ + uint32_t cnt; + cnt = remains / timer->delay_resolution_ns; + val |= ((cnt >> 2) << 21) & E1000_EITR_ITR_CNT; + } + } + + return val; } static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) @@ -3047,8 +3068,24 @@ igb_set_eitr(IGBCore *core, int index, uint32_t val) trace_igb_irq_eitr_set(eitr_num, val); - core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR; - core->mac[index] = val & 0x7FFE; + if (val & E1000_EITR_LLI_EN) { + qemu_log_mask(LOG_UNIMP, "%s: LLI moderation not supported, ignoring\n", + __func__); + } + + if (!(val & E1000_EITR_CNT_IGNR)) { + IGBIntrDelayTimer *timer = &core->eitr[eitr_num]; + uint32_t itr_cnt = (val & E1000_EITR_ITR_CNT) >> 21; + /* CNT is the most significant 10 of 12 bits */ + uint64_t ns = (itr_cnt << 2) * timer->delay_resolution_ns; + + igb_intrmgr_arm_timer(timer, ns); + } + + val &= E1000_EITR_INTERVAL | E1000_EITR_LLI_EN; + + core->mac[index] = val; + core->eitr_guest_value[eitr_num] = val; } static void