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[124.169.212.233]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72daba511a4sm2235950b3a.140.2025.01.17.09.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 09:23:10 -0800 (PST) From: Nicholas Piggin To: Fabiano Rosas Cc: Nicholas Piggin , John Snow , Laurent Vivier , Paolo Bonzini , Akihiko Odaki , "Michael S . Tsirkin" , Marcel Apfelbaum , qemu-block@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 4/4] qtest/libqos/pci: Factor msix entry helpers into pci common code Date: Sat, 18 Jan 2025 03:22:43 +1000 Message-ID: <20250117172244.406206-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250117172244.406206-1-npiggin@gmail.com> References: <20250117172244.406206-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=npiggin@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Setting msix entry address and data and masking is moved into common code helpers from virtio tests. For now that remains the only user, but there are changes under development to enable msix vectors for msix, e1000e, and xhci tests, which can make use of them. Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 3 ++ tests/qtest/libqos/pci.c | 53 +++++++++++++++++++++++++++++++++ tests/qtest/libqos/virtio-pci.c | 48 ++++------------------------- 3 files changed, 61 insertions(+), 43 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 5a7b2454ad5..d46ce4239f0 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -93,8 +93,11 @@ void qpci_device_enable(QPCIDevice *dev); uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr); void qpci_msix_enable(QPCIDevice *dev); void qpci_msix_disable(QPCIDevice *dev); +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data); bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked); uint16_t qpci_msix_table_size(QPCIDevice *dev); uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset); diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index a187349d30a..47632c4b403 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -353,6 +353,25 @@ void qpci_msix_disable(QPCIDevice *dev) dev->msix_pba_off = 0; } +void qpci_msix_set_entry(QPCIDevice *dev, uint16_t entry, + uint64_t guest_addr, uint32_t data) +{ + uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_LOWER_ADDR, guest_addr & ~0UL); + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_UPPER_ADDR, + (guest_addr >> 32) & ~0UL); + + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_DATA, data); +} + bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) { uint32_t pba_entry; @@ -360,6 +379,9 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4; g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off); return (pba_entry & (1 << bit_n)) != 0; } @@ -371,6 +393,9 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); g_assert_cmphex(addr, !=, 0); val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); @@ -384,6 +409,34 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) } } +void qpci_msix_set_masked(QPCIDevice *dev, uint16_t entry, bool masked) +{ + uint8_t addr; + uint16_t val; + uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE; + + g_assert(dev->msix_enabled); + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(dev)); + + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); + g_assert_cmphex(addr, !=, 0); + val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + g_assert(!(val & PCI_MSIX_FLAGS_MASKALL)); + + val = qpci_io_readl(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL); + if (masked && !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val | PCI_MSIX_ENTRY_CTRL_MASKBIT); + } else if (!masked && (val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { + qpci_io_writel(dev, dev->msix_table_bar, + vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL, + val & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + } +} + uint16_t qpci_msix_table_size(QPCIDevice *dev) { uint8_t addr; diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c index 2b59fb181c9..ed7f50e41a5 100644 --- a/tests/qtest/libqos/virtio-pci.c +++ b/tests/qtest/libqos/virtio-pci.c @@ -318,64 +318,26 @@ void qvirtio_pci_device_disable(QVirtioPCIDevice *d) void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, QGuestAllocator *alloc, uint16_t entry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off = d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); vqpci->msix_entry = entry; - vqpci->msix_addr = guest_alloc(alloc, 4); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (vqpci->msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data); - - control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + qpci_msix_set_entry(d->pdev, entry, vqpci->msix_addr, vqpci->msix_data); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_queue_vector(d, vqpci->vq.index, entry); } void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, QGuestAllocator *alloc, uint16_t entry) { - uint32_t control; - uint64_t off; - g_assert(d->pdev->msix_enabled); - off = d->pdev->msix_table_off + (entry * 16); - - g_assert_cmpint(entry, >=, 0); - g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); d->config_msix_entry = entry; - d->config_msix_data = 0x12345678; d->config_msix_addr = guest_alloc(alloc, 4); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_UPPER_ADDR, - (d->config_msix_addr >> 32) & ~0UL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_DATA, d->config_msix_data); - - control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL); - qpci_io_writel(d->pdev, d->pdev->msix_table_bar, - off + PCI_MSIX_ENTRY_VECTOR_CTRL, - control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); - + qpci_msix_set_entry(d->pdev, entry, d->config_msix_addr, + d->config_msix_data); + qpci_msix_set_masked(d->pdev, entry, false); d->msix_ops->set_config_vector(d, entry); }