diff mbox series

[PULL,v2,07/50] target/riscv: add shvstvecd

Message ID	20250119011225.11452-8-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL v2 07/50] target/riscv: add shvstvecd Date: Sun, 19 Jan 2025 11:11:42 +1000 Message-ID: <20250119011225.11452-8-alistair.francis@wdc.com> In-Reply-To: <20250119011225.11452-1-alistair.francis@wdc.com> References: <20250119011225.11452-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names \| expand [PULL,v2,01/50] target/riscv: rvv: fix typo in vext continuous ldst function names [PULL,v2,02/50] target/riscv: rvv: speed up small unit-stride loads and stores [PULL,v2,03/50] riscv/gdbstub: add V bit to priv reg [PULL,v2,04/50] target/riscv: add shcounterenw [PULL,v2,05/50] target/riscv: add shvstvala [PULL,v2,06/50] target/riscv: add shtvala [PULL,v2,07/50] target/riscv: add shvstvecd [PULL,v2,08/50] target/riscv: add shvsatpa [PULL,v2,09/50] target/riscv: add shgatpa [PULL,v2,10/50] target/riscv/tcg: add sha [PULL,v2,11/50] target/riscv: use RISCVException enum in exception helpers [PULL,v2,12/50] target/riscv: add trace in riscv_raise_exception() [PULL,v2,13/50] target/riscv: Remove obsolete pointer masking extension code. [PULL,v2,14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 [PULL,v2,15/50] target/riscv: Add helper functions to calculate current number of masked bits for p… [PULL,v2,16/50] target/riscv: Add pointer masking tb flags [PULL,v2,17/50] target/riscv: Update address modify functions to take into account pointer masking [PULL,v2,18/50] target/riscv: Apply pointer masking for virtualized memory accesses [PULL,v2,19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer … [PULL,v2,20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig [PULL,v2,21/50] target/riscv: Add Smrnmi CSRs [PULL,v2,22/50] target/riscv: Handle Smrnmi interrupt and exception [PULL,v2,23/50] target/riscv: Add Smrnmi mnret instruction [PULL,v2,24/50] target/riscv: Add Smrnmi cpu extension [PULL,v2,25/50] target/riscv: Add Zicfilp support for Smrnmi [PULL,v2,26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu [PULL,v2,27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu [PULL,v2,28/50] target/riscv: Add properties for Indirect CSR Access extension [PULL,v2,29/50] target/riscv: Decouple AIA processing from xiselect and xireg [PULL,v2,30/50] target/riscv: Enable S*stateen bits for AIA [PULL,v2,31/50] target/riscv: Support generic CSR indirect access [PULL,v2,32/50] target/riscv: Add properties for counter delegation ISA extensions [PULL,v2,33/50] target/riscv: Add counter delegation definitions [PULL,v2,34/50] target/riscv: Add select value range check for counter delegation [PULL,v2,35/50] target/riscv: Add counter delegation/configuration support [PULL,v2,36/50] target/riscv: Invoke pmu init after feature enable [PULL,v2,37/50] target/riscv: Add implied rule for counter delegation extensions [PULL,v2,38/50] target/riscv: Add configuration for S[m\|s]csrind, Smcdeleg/Ssccfg [PULL,v2,39/50] target/riscv: Fix henvcfg potentially containing stale bits [PULL,v2,40/50] target/riscv: Add Ssdbltrp CSRs handling [PULL,v2,41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior [PULL,v2,42/50] target/riscv: Implement Ssdbltrp exception handling [PULL,v2,43/50] target/riscv: Add Ssdbltrp ISA extension enable switch [PULL,v2,44/50] target/riscv: Add Smdbltrp CSRs handling [PULL,v2,45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior [PULL,v2,46/50] target/riscv: Implement Smdbltrp behavior [PULL,v2,47/50] target/riscv: Add Smdbltrp ISA extension enable switch [PULL,v2,48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache [PULL,v2,49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0 [PULL,v2,50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

Commit Message

Alistair Francis Jan. 19, 2025, 1:11 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

shvstvecd is defined in RVA22 as:

"vstvec.MODE must be capable of holding the value 0 (Direct).
When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any
valid four-byte-aligned address."

This is always true for TCG so let's claim support for it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c                |   1 +
 tests/data/acpi/riscv64/virt/RHCT | Bin 364 -> 374 bytes
 2 files changed, 1 insertion(+)

diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index 065f894010..2c7dc6c9ab 100644
Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/riscv64/virt/RHCT differ

diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fe5f7b572f..20cbb6b2f4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -186,6 +186,7 @@  const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
+    ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
     ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
     ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),