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(unknown [10.167.135.44]) by edo.cn.fujitsu.com (Postfix) with ESMTP id 5C8891A0071; Mon, 20 Jan 2025 11:09:55 +0800 (CST) To: qemu-devel@nongnu.org Cc: Jonathan Cameron , Fan Ni , linux-cxl@vger.kernel.org, Li Zhijian Subject: [PATCH 1/3] hw/mem/cxl_type3: Add paired msix_uninit_exclusive_bar() call Date: Mon, 20 Jan 2025 11:09:45 +0800 Message-Id: <20250120030947.254930-1-lizhijian@fujitsu.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSS-9.1.0.1417-9.0.0.1002-28934.004 X-TM-AS-User-Approved-Sender: Yes X-TMASE-Version: IMSS-9.1.0.1417-9.0.1002-28934.004 X-TMASE-Result: 10-0.176100-10.000000 X-TMASE-MatchedRID: toN6SH028bUy7r9tI4sSuomfV7NNMGm+1GdxOr7L6H2u9yzHHu0ZiSZl e49VkKqHIvrftAIhWmLy9zcRSkKatXwzxAv8kID0zr16YOzjZ13QiNv55aRoGrqln+jYe7Zh17f TaRrC7JloAzXI4Nhg5341niV9KymzHxPMjOKY7A/+HHE8LDNSg8RB0bsfrpPIcSqbxBgG0w4cPL OQ+phrrYqdbFd4X7QAKvPEkuwr1iSKfjOIOfJrLtIq+VrwLz72zNQ3fXMkh2SDToamn92pqqZUo ggwSSPywmvPT4lO6OdbjBuldNvkMkoq97WSHdFjfupJaud1uZCfRs6uIbkFVw== X-TMASE-SNAP-Result: 1.821001.0001-0-1-22:0,33:0,34:0-0 Received-SPF: pass client-ip=139.138.61.253; envelope-from=lizhijian@fujitsu.com; helo=esa8.hc1455-7.c3s2.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Li Zhijian X-Patchwork-Original-From: Li Zhijian via From: Li Zhijian Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org msix_uninit_exclusive_bar() should be paired with msix_init_exclusive_bar() Ensure proper resource cleanup by adding the missing `msix_uninit_exclusive_bar()` call for the Type3 CXL device. Signed-off-by: Li Zhijian --- hw/mem/cxl_type3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index f64af19ed6ae..9dad250f56d5 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -936,6 +936,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) err_release_cdat: cxl_doe_cdat_release(cxl_cstate); err_free_special_ops: + msix_uninit_exclusive_bar(pci_dev); g_free(regs->special_ops); err_address_space_free: if (ct3d->dc.host_dc) { @@ -959,6 +960,7 @@ static void ct3_exit(PCIDevice *pci_dev) pcie_aer_exit(pci_dev); cxl_doe_cdat_release(cxl_cstate); + msix_uninit_exclusive_bar(pci_dev); g_free(regs->special_ops); if (ct3d->dc.host_dc) { cxl_destroy_dc_regions(ct3d);