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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322ad74sm13989453f8f.56.2025.01.21.08.18.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Jan 2025 08:18:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , Aurelien Jarno Subject: [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Date: Tue, 21 Jan 2025 17:18:14 +0100 Message-ID: <20250121161817.33654-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250121161817.33654-1-philmd@linaro.org> References: <20250121161817.33654-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The MIPS timer and IRQs are tied to the CPU. Creating them outside in board code isn't correct. Do it once in the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/cps.c | 4 ---- hw/mips/fuloong2e.c | 4 ---- hw/mips/jazz.c | 4 ---- hw/mips/loongson3_virt.c | 4 ---- hw/mips/malta.c | 4 ---- hw/mips/mipssim.c | 4 ---- target/mips/cpu.c | 5 +++++ 7 files changed, 5 insertions(+), 24 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 0d8cbdc8924..f85fb4458af 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -91,10 +91,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) return; } - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 160ceb769dc..9a638f596bd 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -277,10 +277,6 @@ static void mips_fuloong2e_init(MachineState *machine) } } - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* North bridge, Bonito --> IP2 */ pci_bus = bonito_init(env->irq[2]); diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index c89610639a9..ce4a702aa53 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -259,10 +259,6 @@ static void mips_jazz_init(MachineState *machine, exit(1); } - /* Init CPU internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* Chipset */ rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); sysbus = SYS_BUS_DEVICE(rc4030); diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index f3cc7a8376f..91070824bbe 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -568,10 +568,6 @@ static void mips_loongson3_virt_init(MachineState *machine) /* init CPUs */ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); - - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); if (!kvm_enabled()) { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4e9cccaa347..ac3b16229c8 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1037,10 +1037,6 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s, for (i = 0; i < ms->smp.cpus; i++) { cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, TARGET_BIG_ENDIAN); - - /* Init internal devices */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); } diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index a294779a82b..d4b3b043053 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -203,10 +203,6 @@ mips_mipssim_init(MachineState *machine) reset_info->vector = load_kernel(); } - /* Init CPU internal devices. */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - /* * Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts * (except for the hardcoded serial port interrupt) -device cannot work, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 028a3c91afb..95df8985bc6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -476,6 +476,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) fpu_init(env, env->cpu_model); mvp_init(env); + /* Init internal devices */ +#ifndef CONFIG_USER_ONLY + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); +#endif if (!clock_get(cpu->clock)) { #ifndef CONFIG_USER_ONLY if (!qtest_enabled()) {