Message ID | 20250121184847.2109128-3-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | target/riscv: Coverity fixes | expand |
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab209d0cda..0e83c3b045 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2697,15 +2697,10 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, } else if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) { return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); - } else { - return RISCV_EXCP_ILLEGAL_INST; } done: - if (ret) { - return RISCV_EXCP_ILLEGAL_INST; - } - return RISCV_EXCP_NONE; + return RISCV_EXCP_ILLEGAL_INST; } static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,