From patchwork Fri Jan 24 13:20:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13949450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0881FC0218B for ; Fri, 24 Jan 2025 13:41:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tbJvb-0004F3-5A; Fri, 24 Jan 2025 08:40:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tbJup-0001U2-A4 for qemu-devel@nongnu.org; Fri, 24 Jan 2025 08:40:13 -0500 Received: from mgamail.intel.com ([198.175.65.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tbJul-00041c-TN for qemu-devel@nongnu.org; Fri, 24 Jan 2025 08:40:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737726004; x=1769262004; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DiFlJ2bW4l04b5XDYk9TOAHCOXgmdgi5M+5gwbsLQjI=; b=GMkvSezC4LMCHVtIA5/JK29LitSHThYN+B5cB5/u36Wsg3HjTmN5cF0H mjvWQAKPRUDbb+zmb/thJrppVNEtrJE4lj/b79YeM43pnt7+FOeJ+xExS p9DcA1flbd8jyLzi9egYQb95SioDFyp6ATe8TITQiPzq048IKIP5L7+EU v75vsr3I+kQEWGMPX1zsL8kcwsZqASbTxtP5SJAHhc5nzJq/Ar3UWE1HR 59yXMib1PNyg/sjQNRmuyAxCIUHmg9X24z1fiws5RBRtUcK+EvhkXrjOM 48ybD2U3LUAEK54KKE20wWrQok8U0ib6ebV6KCrjP3G4jgyFAxMQhXl4i A==; X-CSE-ConnectionGUID: 51pXrfGdTS+LPX8yFJbHqw== X-CSE-MsgGUID: UBueNirSQHmMpozKIGM9lw== X-IronPort-AV: E=McAfee;i="6700,10204,11325"; a="49246580" X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="49246580" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 05:39:44 -0800 X-CSE-ConnectionGUID: lmzWCOrORrm/jSDeiiD8Bw== X-CSE-MsgGUID: P0tFgi7SR3a/PtpBq3Nojw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="111804457" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa003.fm.intel.com with ESMTP; 24 Jan 2025 05:39:40 -0800 From: Xiaoyao Li To: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Igor Mammedov Cc: Zhao Liu , "Michael S. Tsirkin" , Eric Blake , Markus Armbruster , Peter Maydell , Marcelo Tosatti , Huacai Chen , Rick Edgecombe , Francesco Lavra , xiaoyao.li@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 43/52] i386/tdx: Mask off CPUID bits by unsupported TD Attributes Date: Fri, 24 Jan 2025 08:20:39 -0500 Message-Id: <20250124132048.3229049-44-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250124132048.3229049-1-xiaoyao.li@intel.com> References: <20250124132048.3229049-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=198.175.65.13; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -63 X-Spam_score: -6.4 X-Spam_bar: ------ X-Spam_report: (-6.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For TDX, some CPUID feature bit is configured via TD attributes. Adjust the supported CPUID to mask off the bit if its matched attribute is unsupported. Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 4 ++++ target/i386/kvm/tdx.c | 54 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8b63685e64e1..4890424c3a9e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -905,6 +905,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_0_ECX_LA57 (1U << 16) /* Read Processor ID */ #define CPUID_7_0_ECX_RDPID (1U << 22) +/* KeyLocker */ +#define CPUID_7_0_ECX_KeyLocker (1U << 23) /* Bus Lock Debug Exception */ #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) /* Cache Line Demote Instruction */ @@ -957,6 +959,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* Linear address space separation */ +#define CPUID_7_1_EAX_LASS (1U << 6) /* CMPCCXADD Instructions */ #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) /* Fast Zero REP MOVS */ diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 2d493a0dc1c6..3997a439f054 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -527,6 +527,58 @@ KvmCpuidInfo tdx_fixed1_bits = { }, }; +typedef struct TdxAttrsMap { + uint32_t attr_index; + uint32_t cpuid_leaf; + uint32_t cpuid_subleaf; + int cpuid_reg; + uint32_t feat_mask; +} TdxAttrsMap; + +static TdxAttrsMap tdx_attrs_maps[] = { + {.attr_index = 27, + .cpuid_leaf = 7, + .cpuid_subleaf = 1, + .cpuid_reg = R_EAX, + .feat_mask = CPUID_7_1_EAX_LASS}, + {.attr_index = 30, + .cpuid_leaf = 7, + .cpuid_subleaf = 0, + .cpuid_reg = R_ECX, + .feat_mask = CPUID_7_0_ECX_PKS,}, + {.attr_index = 31, + .cpuid_leaf = 7, + .cpuid_subleaf = 0, + .cpuid_reg = R_ECX, + .feat_mask = CPUID_7_0_ECX_KeyLocker, + }, +}; + +static void tdx_mask_cpuid_by_attrs(uint32_t feature, uint32_t index, + int reg, uint32_t *value) +{ + TdxAttrsMap *map; + uint64_t unavail = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(tdx_attrs_maps); i++) { + map = &tdx_attrs_maps[i]; + + if (feature != map->cpuid_leaf || index != map->cpuid_subleaf || + reg != map->cpuid_reg) { + continue; + } + + if (!((1ULL << map->attr_index) & tdx_caps->supported_attrs)) { + unavail |= map->feat_mask; + } + } + + if (unavail) { + *value &= ~unavail; + } +} + static uint32_t tdx_adjust_cpuid_features(X86ConfidentialGuest *cg, uint32_t feature, uint32_t index, int reg, uint32_t value) @@ -560,6 +612,8 @@ static uint32_t tdx_adjust_cpuid_features(X86ConfidentialGuest *cg, break; } + tdx_mask_cpuid_by_attrs(feature, index, reg, &value); + e = cpuid_find_entry(&tdx_fixed0_bits.cpuid, feature, index); if (e) { fixed0 = cpuid_entry_get_reg(e, reg);