@@ -189,13 +189,13 @@ void cpu_init_fp_statuses(CPUX86State *env)
set_float_default_nan_pattern(0b11000000, &env->mmx_status);
set_float_default_nan_pattern(0b11000000, &env->sse_status);
/*
- * TODO: x86 does flush-to-zero detection after rounding (the SDM
+ * x86 does flush-to-zero detection after rounding (the SDM
* section 10.2.3.3 on the FTZ bit of MXCSR says that we flush
* when we detect underflow, which x86 does after rounding).
*/
- set_float_detect_ftz(detect_ftz_before_rounding, &env->fp_status);
- set_float_detect_ftz(detect_ftz_before_rounding, &env->mmx_status);
- set_float_detect_ftz(detect_ftz_before_rounding, &env->sse_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->fp_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->mmx_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->sse_status);
}
static inline uint8_t save_exception_flags(CPUX86State *env)
@@ -79,14 +79,9 @@ static testdata tests[] = {
/*
* Flushing of denormal outputs to zero should also happen after
* rounding, so setting FTZ should not affect the result or the flags.
- * QEMU currently does not emulate this correctly because we do the
- * flush-to-zero check before rounding, so we incorrectly produce a
- * zero result and set Underflow as well as Precision.
*/
-#ifdef ENABLE_FAILING_TESTS
{ 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true,
0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */
-#endif
};
int main(void)
The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we flush outputs to zero when we detect underflow, which is after rounding. Set the detect_ftz flag accordingly. This allows us to enable the test in fma.c which checks this behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/i386/tcg/fpu_helper.c | 8 ++++---- tests/tcg/x86_64/fma.c | 5 ----- 2 files changed, 4 insertions(+), 9 deletions(-)