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[09/12] target/riscv: handle vwadd.wv form mask and source overlap

Message ID 20250126072056.4004912-10-antonb@tenstorrent.com (mailing list archive)
State New
Headers show
Series target/riscv: Fix some RISC-V instruction corner cases | expand

Commit Message

Anton Blanchard Jan. 26, 2025, 7:20 a.m. UTC 
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 45b2868c54..2309d9abd0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -548,6 +548,7 @@  static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ds(s, vd, vs1, vm) &&
+           require_vm(vm, vs2) &&
            require_align(vs2, s->lmul + 1);
 }