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[06/12] target/riscv: handle vzext.vf2 form mask and source overlap

Message ID 20250126072056.4004912-7-antonb@tenstorrent.com (mailing list archive)
State New
Headers show
Series target/riscv: Fix some RISC-V instruction corner cases | expand

Commit Message

Anton Blanchard Jan. 26, 2025, 7:20 a.m. UTC 
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index a873536eea..0952bcbe2c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3631,6 +3631,7 @@  static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
         require_align(a->rd, s->lmul) &&
         require_align(a->rs2, s->lmul - div) &&
         require_vm(a->vm, a->rd) &&
+        require_vm(a->vm, a->rs2) &&
         require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
     return ret;
 }