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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d865sm11029825f8f.38.2025.01.27.03.54.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Jan 2025 03:54:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Paolo Bonzini , qemu-riscv@nongnu.org, Peter Maydell , Richard Henderson , Thomas Huth , qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 05/10] target/mips: Set disassemble_info::endian value in disas_set_info() Date: Mon, 27 Jan 2025 12:54:21 +0100 Message-ID: <20250127115426.51355-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250127115426.51355-1-philmd@linaro.org> References: <20250127115426.51355-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- target/mips/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0b267d2e507..f6d247b530f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -429,12 +429,15 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { #if TARGET_BIG_ENDIAN + info->endian = BFD_ENDIAN_BIG; info->print_insn = print_insn_big_mips; #else + info->endian = BFD_ENDIAN_LITTLE; info->print_insn = print_insn_little_mips; #endif } else { info->print_insn = print_insn_nanomips; + info->endian = BFD_ENDIAN_LITTLE; } }