| Message ID | 20250128060546.1374394-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | MAINTAINERS: Remove Bin Meng from RISC-V maintainers | expand |
On Tue, Jan 28, 2025 at 4:05 PM Alistair Francis <alistair23@gmail.com> wrote: > > Bin Meng has been a long time contributor and maintainer for QEMU RISC-V > and has been very beneficial to the RISC-V ecosystem. > > Unfortunately his email has started to bounce so this patch is removing > them from MAINTAINERS. If in the future Bin Meng wants to return we will > happily re-add them. > > Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> + bmeng.cn@gmail.com to keep you in the loop Alistair
Cc'ing work email On 28/1/25 07:05, Alistair Francis wrote: > Bin Meng has been a long time contributor and maintainer for QEMU RISC-V > and has been very beneficial to the RISC-V ecosystem. > > Unfortunately his email has started to bounce so this patch is removing > them from MAINTAINERS. If in the future Bin Meng wants to return we will > happily re-add them. > > Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > MAINTAINERS | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7be3d8f431..a0e305aa99 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -318,7 +318,6 @@ F: tests/functional/test_ppc_74xx.py > RISC-V TCG CPUs > M: Palmer Dabbelt <palmer@dabbelt.com> > M: Alistair Francis <alistair.francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > R: Weiwei Li <liwei1518@gmail.com> > R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > @@ -1599,7 +1598,6 @@ F: include/hw/riscv/opentitan.h > F: include/hw/*/ibex_*.h > > Microchip PolarFire SoC Icicle Kit > -M: Bin Meng <bmeng.cn@gmail.com> > L: qemu-riscv@nongnu.org > S: Supported > F: docs/system/riscv/microchip-icicle-kit.rst > @@ -1626,7 +1624,6 @@ F: include/hw/char/shakti_uart.h > > SiFive Machines > M: Alistair Francis <Alistair.Francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > @@ -3721,7 +3718,7 @@ S: Orphan > F: hw/i386/amd_iommu.? > > OpenSBI Firmware > -M: Bin Meng <bmeng.cn@gmail.com> > +L: qemu-riscv@nongnu.org > S: Supported > F: pc-bios/opensbi-* > F: .gitlab-ci.d/opensbi.yml
On 1/28/25 3:05 AM, Alistair Francis wrote: > Bin Meng has been a long time contributor and maintainer for QEMU RISC-V > and has been very beneficial to the RISC-V ecosystem. > > Unfortunately his email has started to bounce so this patch is removing > them from MAINTAINERS. If in the future Bin Meng wants to return we will > happily re-add them. > > Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- For the record I tried to contact Bin Jan 16th, using the following emails, about the bouncing of his gmail: - bin.meng@windriver.com - bmeng@tinylab.org Still no reply as of this writing. The better course of action seems to be just remove him for now and add him back once the situation is solved. He can then choose to keep using the gmail or another email of his preference. Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > MAINTAINERS | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7be3d8f431..a0e305aa99 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -318,7 +318,6 @@ F: tests/functional/test_ppc_74xx.py > RISC-V TCG CPUs > M: Palmer Dabbelt <palmer@dabbelt.com> > M: Alistair Francis <alistair.francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > R: Weiwei Li <liwei1518@gmail.com> > R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > @@ -1599,7 +1598,6 @@ F: include/hw/riscv/opentitan.h > F: include/hw/*/ibex_*.h > > Microchip PolarFire SoC Icicle Kit > -M: Bin Meng <bmeng.cn@gmail.com> > L: qemu-riscv@nongnu.org > S: Supported > F: docs/system/riscv/microchip-icicle-kit.rst > @@ -1626,7 +1624,6 @@ F: include/hw/char/shakti_uart.h > > SiFive Machines > M: Alistair Francis <Alistair.Francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > @@ -3721,7 +3718,7 @@ S: Orphan > F: hw/i386/amd_iommu.? > > OpenSBI Firmware > -M: Bin Meng <bmeng.cn@gmail.com> > +L: qemu-riscv@nongnu.org > S: Supported > F: pc-bios/opensbi-* > F: .gitlab-ci.d/opensbi.yml
On Tue, Jan 28, 2025 at 4:05 PM Alistair Francis <alistair23@gmail.com> wrote: > > Bin Meng has been a long time contributor and maintainer for QEMU RISC-V > and has been very beneficial to the RISC-V ecosystem. > > Unfortunately his email has started to bounce so this patch is removing > them from MAINTAINERS. If in the future Bin Meng wants to return we will > happily re-add them. > > Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > MAINTAINERS | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7be3d8f431..a0e305aa99 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -318,7 +318,6 @@ F: tests/functional/test_ppc_74xx.py > RISC-V TCG CPUs > M: Palmer Dabbelt <palmer@dabbelt.com> > M: Alistair Francis <alistair.francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > R: Weiwei Li <liwei1518@gmail.com> > R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > @@ -1599,7 +1598,6 @@ F: include/hw/riscv/opentitan.h > F: include/hw/*/ibex_*.h > > Microchip PolarFire SoC Icicle Kit > -M: Bin Meng <bmeng.cn@gmail.com> > L: qemu-riscv@nongnu.org > S: Supported > F: docs/system/riscv/microchip-icicle-kit.rst > @@ -1626,7 +1624,6 @@ F: include/hw/char/shakti_uart.h > > SiFive Machines > M: Alistair Francis <Alistair.Francis@wdc.com> > -M: Bin Meng <bmeng.cn@gmail.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > @@ -3721,7 +3718,7 @@ S: Orphan > F: hw/i386/amd_iommu.? > > OpenSBI Firmware > -M: Bin Meng <bmeng.cn@gmail.com> > +L: qemu-riscv@nongnu.org > S: Supported > F: pc-bios/opensbi-* > F: .gitlab-ci.d/opensbi.yml > -- > 2.48.1 >
diff --git a/MAINTAINERS b/MAINTAINERS index 7be3d8f431..a0e305aa99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -318,7 +318,6 @@ F: tests/functional/test_ppc_74xx.py RISC-V TCG CPUs M: Palmer Dabbelt <palmer@dabbelt.com> M: Alistair Francis <alistair.francis@wdc.com> -M: Bin Meng <bmeng.cn@gmail.com> R: Weiwei Li <liwei1518@gmail.com> R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> @@ -1599,7 +1598,6 @@ F: include/hw/riscv/opentitan.h F: include/hw/*/ibex_*.h Microchip PolarFire SoC Icicle Kit -M: Bin Meng <bmeng.cn@gmail.com> L: qemu-riscv@nongnu.org S: Supported F: docs/system/riscv/microchip-icicle-kit.rst @@ -1626,7 +1624,6 @@ F: include/hw/char/shakti_uart.h SiFive Machines M: Alistair Francis <Alistair.Francis@wdc.com> -M: Bin Meng <bmeng.cn@gmail.com> M: Palmer Dabbelt <palmer@dabbelt.com> L: qemu-riscv@nongnu.org S: Supported @@ -3721,7 +3718,7 @@ S: Orphan F: hw/i386/amd_iommu.? OpenSBI Firmware -M: Bin Meng <bmeng.cn@gmail.com> +L: qemu-riscv@nongnu.org S: Supported F: pc-bios/opensbi-* F: .gitlab-ci.d/opensbi.yml
Bin Meng has been a long time contributor and maintainer for QEMU RISC-V and has been very beneficial to the RISC-V ecosystem. Unfortunately his email has started to bounce so this patch is removing them from MAINTAINERS. If in the future Bin Meng wants to return we will happily re-add them. Note that I'm not removing Bin Meng as a "SD (Secure Card)" maintainer. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- MAINTAINERS | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)