| Message ID | 20250203173040.145763-3-Jonathan.Cameron@huawei.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm/virt: CXL support via pxb_cxl | expand |
Jonathan, > On Feb 4, 2025, at 2:30, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > Add a single complex case for aarch64 virt machine. > Given existing much more comprehensive tests for x86 cover the > common functionality, a single test should be enough to verify > that the aarch64 part continue to work. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > tests/qtest/cxl-test.c | 59 ++++++++++++++++++++++++++++++++--------- > tests/qtest/meson.build | 1 + > 2 files changed, 47 insertions(+), 13 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index a600331843..c7189d6222 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -19,6 +19,12 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on -cpu max " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > + > #define QEMU_RP \ > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) > qtest_end(); > rmdir(tmpfs); > } > + > +static void cxl_virt_2pxb_4rp_4t3d(void) > +{ > + g_autoptr(GString) cmdline = g_string_new(NULL); > + char template[] = "/tmp/cxl-test-XXXXXX"; > + const char *tmpfs; > + > + tmpfs = mkdtemp(template); > + > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > + tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + rmdir(tmpfs); > +} > #endif /* CONFIG_POSIX */ > > int main(int argc, char **argv) > { > - g_test_init(&argc, &argv, NULL); > + const char *arch = qtest_get_arch(); > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + g_test_init(&argc, &argv, NULL); > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > #ifdef CONFIG_POSIX > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > + cxl_2pxb_4rp_4t3d); > #endif > + } else if (strcmp(arch, "aarch64") == 0) { > +#ifdef CONFIG_POSIX > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > + cxl_virt_2pxb_4rp_4t3d); > +#endif > + } > + > return g_test_run(); > } > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index e60e92fe9d..f5e7fb060e 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -257,6 +257,7 @@ qtests_aarch64 = \ > (config_all_accel.has_key('CONFIG_TCG') and \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ > + qtests_cxl + \ > ['arm-cpu-features', > 'numa-test', > 'boot-serial-test', > -- > 2.43.0 > In Ubuntu 22.04 LTS, cxl-test applied on top of today’s QEMU upstream master branch cxl-test fails: $ ./tests/qtest/cxl-test # random seed: R02S2a8b02df7b32b79d086ce22f7f8ebeab 1..1 # Start of aarch64 tests # Start of pci tests # Start of cxl tests # Start of virt tests # starting QEMU: exec qemu-system-aarch64 -qtest unix:/tmp/qtest-568421.sock -qtest-log /dev/null -chardev socket,path=/tmp/qtest-568421.qmp,id=char0 -mon chardev=char0,mode=control -display none -audio none -machine virt,cxl=on -cpu max -device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 -device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 -M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G -device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 -device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 -device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 -device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 -object memory-backend-file,id=cxl-mem0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp0,persistent-memdev=cxl-mem0,lsa=lsa0,id=pmem0 -object memory-backend-file,id=cxl-mem1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1,id=pmem1 -object memory-backend-file,id=cxl-mem2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp2,persistent-memdev=cxl-mem2,lsa=lsa2,id=pmem2 -object memory-backend-file,id=cxl-mem3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp3,persistent-memdev=cxl-mem3,lsa=lsa3,id=pmem3 -accel qtest qemu-system-aarch64: -audio: invalid option socket_accept failed: Resource temporarily unavailable ** ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) Bail out! ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) ../tests/qtest/libqtest.c:199: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) Aborted (core dumped) Do I need set env vars when execute this test? Itaru.
On Tue, 4 Feb 2025 14:16:19 +0900 Itaru Kitayama <itaru.kitayama@linux.dev> wrote: > Jonathan, > > > On Feb 4, 2025, at 2:30, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > > > Add a single complex case for aarch64 virt machine. > > Given existing much more comprehensive tests for x86 cover the > > common functionality, a single test should be enough to verify > > that the aarch64 part continue to work. > > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > > tests/qtest/cxl-test.c | 59 ++++++++++++++++++++++++++++++++--------- > > tests/qtest/meson.build | 1 + > > 2 files changed, 47 insertions(+), 13 deletions(-) > > > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > > index a600331843..c7189d6222 100644 > > --- a/tests/qtest/cxl-test.c > > +++ b/tests/qtest/cxl-test.c > > @@ -19,6 +19,12 @@ > > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > > "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > > > +#define QEMU_VIRT_2PXB_CMD \ > > + "-machine virt,cxl=on -cpu max " \ > > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > + > > #define QEMU_RP \ > > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > > > @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) > > qtest_end(); > > rmdir(tmpfs); > > } > > + > > +static void cxl_virt_2pxb_4rp_4t3d(void) > > +{ > > + g_autoptr(GString) cmdline = g_string_new(NULL); > > + char template[] = "/tmp/cxl-test-XXXXXX"; > > + const char *tmpfs; > > + > > + tmpfs = mkdtemp(template); > > + > > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > > + tmpfs, tmpfs); > > + > > + qtest_start(cmdline->str); > > + qtest_end(); > > + rmdir(tmpfs); > > +} > > #endif /* CONFIG_POSIX */ > > > > int main(int argc, char **argv) > > { > > - g_test_init(&argc, &argv, NULL); > > + const char *arch = qtest_get_arch(); > > > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > > - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > > + g_test_init(&argc, &argv, NULL); > > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > > + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > > + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > > #ifdef CONFIG_POSIX > > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); > > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > > + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > > + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > > + cxl_2pxb_4rp_4t3d); > > #endif > > + } else if (strcmp(arch, "aarch64") == 0) { > > +#ifdef CONFIG_POSIX > > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > > + cxl_virt_2pxb_4rp_4t3d); > > +#endif > > + } > > + > > return g_test_run(); > > } > > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > > index e60e92fe9d..f5e7fb060e 100644 > > --- a/tests/qtest/meson.build > > +++ b/tests/qtest/meson.build > > @@ -257,6 +257,7 @@ qtests_aarch64 = \ > > (config_all_accel.has_key('CONFIG_TCG') and \ > > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ > > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ > > + qtests_cxl + \ > > ['arm-cpu-features', > > 'numa-test', > > 'boot-serial-test', > > -- > > 2.43.0 > > > > In Ubuntu 22.04 LTS, cxl-test applied on top of today’s QEMU upstream master branch cxl-test fails: > > $ ./tests/qtest/cxl-test > # random seed: R02S2a8b02df7b32b79d086ce22f7f8ebeab > 1..1 > # Start of aarch64 tests > # Start of pci tests > # Start of cxl tests > # Start of virt tests > # starting QEMU: exec qemu-system-aarch64 -qtest unix:/tmp/qtest-568421.sock -qtest-log /dev/null -chardev socket,path=/tmp/qtest-568421.qmp,id=char0 -mon chardev=char0,mode=control -display none -audio none -machine virt,cxl=on -cpu max -device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 -device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 -M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G -device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 -device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 -device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 -device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 -object memory-backend-file,id=cxl-mem0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp0,persistent-memdev=cxl-mem0,lsa=lsa0,id=pmem0 -object memory-backend-file,id=cxl-mem1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1,id=pmem1 -object memory-backend-file,id=cxl-mem2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp2,persistent-memdev=cxl-mem2,lsa=lsa2,id=pmem2 -object memory-backend-file,id=cxl-mem3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp3,persistent-memdev=cxl-mem3,lsa=lsa3,id=pmem3 -accel qtest > qemu-system-aarch64: -audio: invalid option > socket_accept failed: Resource temporarily unavailable > ** > ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) > Bail out! ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) > ../tests/qtest/libqtest.c:199: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) > Aborted (core dumped) > > Do I need set env vars when execute this test? I've just been running it with make check-qtest and not seeing anything similar. I'm not sure what infrastructure qtest puts round these but I guess it sets up that socket. Jonathan > > Itaru.
> On Feb 4, 2025, at 18:29, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: > > On Tue, 4 Feb 2025 14:16:19 +0900 > Itaru Kitayama <itaru.kitayama@linux.dev> wrote: > >> Jonathan, >> >>> On Feb 4, 2025, at 2:30, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote: >>> >>> Add a single complex case for aarch64 virt machine. >>> Given existing much more comprehensive tests for x86 cover the >>> common functionality, a single test should be enough to verify >>> that the aarch64 part continue to work. >>> >>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> >>> --- >>> tests/qtest/cxl-test.c | 59 ++++++++++++++++++++++++++++++++--------- >>> tests/qtest/meson.build | 1 + >>> 2 files changed, 47 insertions(+), 13 deletions(-) >>> >>> diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c >>> index a600331843..c7189d6222 100644 >>> --- a/tests/qtest/cxl-test.c >>> +++ b/tests/qtest/cxl-test.c >>> @@ -19,6 +19,12 @@ >>> "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ >>> "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " >>> >>> +#define QEMU_VIRT_2PXB_CMD \ >>> + "-machine virt,cxl=on -cpu max " \ >>> + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ >>> + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ >>> + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " >>> + >>> #define QEMU_RP \ >>> "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " >>> >>> @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) >>> qtest_end(); >>> rmdir(tmpfs); >>> } >>> + >>> +static void cxl_virt_2pxb_4rp_4t3d(void) >>> +{ >>> + g_autoptr(GString) cmdline = g_string_new(NULL); >>> + char template[] = "/tmp/cxl-test-XXXXXX"; >>> + const char *tmpfs; >>> + >>> + tmpfs = mkdtemp(template); >>> + >>> + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, >>> + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, >>> + tmpfs, tmpfs); >>> + >>> + qtest_start(cmdline->str); >>> + qtest_end(); >>> + rmdir(tmpfs); >>> +} >>> #endif /* CONFIG_POSIX */ >>> >>> int main(int argc, char **argv) >>> { >>> - g_test_init(&argc, &argv, NULL); >>> + const char *arch = qtest_get_arch(); >>> >>> - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); >>> - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); >>> - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); >>> - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); >>> - qtest_add_func("/pci/cxl/rp", cxl_root_port); >>> - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); >>> + g_test_init(&argc, &argv, NULL); >>> + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { >>> + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); >>> + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); >>> + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); >>> + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); >>> + qtest_add_func("/pci/cxl/rp", cxl_root_port); >>> + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); >>> #ifdef CONFIG_POSIX >>> - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); >>> - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); >>> - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); >>> - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); >>> - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); >>> - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); >>> + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); >>> + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); >>> + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); >>> + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); >>> + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); >>> + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", >>> + cxl_2pxb_4rp_4t3d); >>> #endif >>> + } else if (strcmp(arch, "aarch64") == 0) { >>> +#ifdef CONFIG_POSIX >>> + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", >>> + cxl_virt_2pxb_4rp_4t3d); >>> +#endif >>> + } >>> + >>> return g_test_run(); >>> } >>> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build >>> index e60e92fe9d..f5e7fb060e 100644 >>> --- a/tests/qtest/meson.build >>> +++ b/tests/qtest/meson.build >>> @@ -257,6 +257,7 @@ qtests_aarch64 = \ >>> (config_all_accel.has_key('CONFIG_TCG') and \ >>> config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ >>> (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ >>> + qtests_cxl + \ >>> ['arm-cpu-features', >>> 'numa-test', >>> 'boot-serial-test', >>> -- >>> 2.43.0 >>> >> >> In Ubuntu 22.04 LTS, cxl-test applied on top of today’s QEMU upstream master branch cxl-test fails: >> >> $ ./tests/qtest/cxl-test >> # random seed: R02S2a8b02df7b32b79d086ce22f7f8ebeab >> 1..1 >> # Start of aarch64 tests >> # Start of pci tests >> # Start of cxl tests >> # Start of virt tests >> # starting QEMU: exec qemu-system-aarch64 -qtest unix:/tmp/qtest-568421.sock -qtest-log /dev/null -chardev socket,path=/tmp/qtest-568421.qmp,id=char0 -mon chardev=char0,mode=control -display none -audio none -machine virt,cxl=on -cpu max -device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 -device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 -M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G -device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 -device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 -device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 -device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 -object memory-backend-file,id=cxl-mem0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa0,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp0,persistent-memdev=cxl-mem0,lsa=lsa0,id=pmem0 -object memory-backend-file,id=cxl-mem1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa1,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1,id=pmem1 -object memory-backend-file,id=cxl-mem2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa2,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp2,persistent-memdev=cxl-mem2,lsa=lsa2,id=pmem2 -object memory-backend-file,id=cxl-mem3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -object memory-backend-file,id=lsa3,mem-path=/tmp/cxl-test-WdBn4X,size=256M -device cxl-type3,bus=rp3,persistent-memdev=cxl-mem3,lsa=lsa3,id=pmem3 -accel qtest >> qemu-system-aarch64: -audio: invalid option >> socket_accept failed: Resource temporarily unavailable >> ** >> ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) >> Bail out! ERROR:../tests/qtest/libqtest.c:550:qtest_connect: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0) >> ../tests/qtest/libqtest.c:199: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) >> Aborted (core dumped) >> >> Do I need set env vars when execute this test? > > I've just been running it with make check-qtest and not seeing anything similar. > Ah. `make check-qtest` rather than directly executing the binary made the updated cxl-test finished with other 26 “Ok” test 1 Skipped for aarch64 Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com <mailto:itaru.kitayama@fujitsu.com>> > I'm not sure what infrastructure qtest puts round these but I guess it sets > up that socket. > > Jonathan > > > >> >> Itaru.
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index a600331843..c7189d6222 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -19,6 +19,12 @@ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " +#define QEMU_VIRT_2PXB_CMD \ + "-machine virt,cxl=on -cpu max " \ + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " + #define QEMU_RP \ "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void) qtest_end(); rmdir(tmpfs); } + +static void cxl_virt_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline = g_string_new(NULL); + char template[] = "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs = mkdtemp(template); + + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); + rmdir(tmpfs); +} #endif /* CONFIG_POSIX */ int main(int argc, char **argv) { - g_test_init(&argc, &argv, NULL); + const char *arch = qtest_get_arch(); - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); - qtest_add_func("/pci/cxl/rp", cxl_root_port); - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + g_test_init(&argc, &argv, NULL); + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", + cxl_2pxb_4rp_4t3d); #endif + } else if (strcmp(arch, "aarch64") == 0) { +#ifdef CONFIG_POSIX + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", + cxl_virt_2pxb_4rp_4t3d); +#endif + } + return g_test_run(); } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index e60e92fe9d..f5e7fb060e 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -257,6 +257,7 @@ qtests_aarch64 = \ (config_all_accel.has_key('CONFIG_TCG') and \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ + qtests_cxl + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test',
Add a single complex case for aarch64 virt machine. Given existing much more comprehensive tests for x86 cover the common functionality, a single test should be enough to verify that the aarch64 part continue to work. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- tests/qtest/cxl-test.c | 59 ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | 1 + 2 files changed, 47 insertions(+), 13 deletions(-)