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[2003:fa:af00:4300:6a2c:ae69:f03f:1c85]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438e23d42c7sm187233595e9.3.2025.02.04.01.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 01:21:36 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Bernhard Beschow , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , Paolo Bonzini Subject: [PATCH v2 14/18] hw/arm/fsl-imx8mp: Add Ethernet controller Date: Tue, 4 Feb 2025 10:21:08 +0100 Message-ID: <20250204092112.26957-15-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250204092112.26957-1-shentey@gmail.com> References: <20250204092112.26957-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=shentey@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one and a Designware one. There is no device model for the latter, so only add the ENET one. Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 8 ++++++++ hw/arm/fsl-imx8mp.c | 24 ++++++++++++++++++++++++ hw/arm/imx8mp-evk.c | 1 + hw/arm/Kconfig | 1 + 5 files changed, 35 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 9293cabb85..4109387b6e 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devices: * 4 UARTs * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller + * 1 Ethernet Controller * 5 GPIO Controllers * 6 I2C Controllers * 3 SPI Controllers diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 975887751b..e292c31a3d 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -17,6 +17,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/net/imx_fec.h" #include "hw/or-irq.h" #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" @@ -58,11 +59,15 @@ struct FslImx8mpState { IMXSPIState spi[FSL_IMX8MP_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; + IMXFECState enet; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; + + uint32_t phy_num; + bool phy_connected; }; enum FslImx8mpMemoryRegions { @@ -253,6 +258,9 @@ enum FslImx8mpIrqs { FSL_IMX8MP_WDOG2_IRQ = 79, FSL_IMX8MP_WDOG3_IRQ = 10, + FSL_IMX8MP_ENET1_MAC_IRQ = 118, + FSL_IMX6_ENET1_MAC_1588_IRQ = 121, + FSL_IMX8MP_PCI_INTA_IRQ = 126, FSL_IMX8MP_PCI_INTB_IRQ = 125, FSL_IMX8MP_PCI_INTC_IRQ = 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 43395df628..665123cf9c 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -243,6 +243,8 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); } + object_initialize_child(obj, "eth0", &s->enet, TYPE_IMX_ENET); + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -546,6 +548,21 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(gicdev, spi_table[i].irq)); } + /* ENET1 */ + object_property_set_uint(OBJECT(&s->enet), "phy-num", s->phy_num, + &error_abort); + object_property_set_uint(OBJECT(&s->enet), "tx-ring-num", 3, &error_abort); + qemu_configure_nic_device(DEVICE(&s->enet), true, NULL); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0, + fsl_imx8mp_memmap[FSL_IMX8MP_ENET1].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MP_ENET1_MAC_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1, + qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IRQ)); + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -608,6 +625,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3: + case FSL_IMX8MP_ENET1: case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE_PHY1: @@ -628,10 +646,16 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) } } +static const Property fsl_imx8mp_properties[] = { + DEFINE_PROP_UINT32("fec1-phy-num", FslImx8mpState, phy_num, 0), + DEFINE_PROP_BOOL("fec1-phy-connected", FslImx8mpState, phy_connected, true), +}; + static void fsl_imx8mp_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + device_class_set_props(dc, fsl_imx8mp_properties); dc->realize = fsl_imx8mp_realize; dc->desc = "i.MX 8M Plus SoC"; diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index 27d9e9e8ee..e1a7892fd7 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -36,6 +36,7 @@ static void imx8mp_evk_init(MachineState *machine) s = FSL_IMX8MP(object_new(TYPE_FSL_IMX8MP)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal); qdev_realize(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX8MP_RAM_START, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f2859f6a88..7767a8725a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -585,6 +585,7 @@ config FSL_IMX8MP select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_FEC select IMX_I2C select OR_IRQ select PCI_EXPRESS_DESIGNWARE