[RFC,1/4] cpu-exec: support single-step without debug

Commit Message

Joelle van Dyne Feb. 9, 2025, 3:32 a.m. UTC

Currently, single-stepping is tied to GDB debugging. This means that when
EXCP_DEBUG is returned, a debug exception is triggered in many cases. We
define a new EXCP_SINGLESTEP to differentiate the case where we want a
single step to not be tied to a debug exception. We also define a new flag
for cpu->singlestep_enabled called SSTEP_NODEBUG which is set when we want
to use single-step for purposes other than debugging.

Signed-off-by: Joelle van Dyne <[e-mail]>
---
 include/exec/cpu-common.h |  1 +
 include/hw/core/cpu.h     |  1 +
 target/arm/internals.h    |  3 ++-
 accel/tcg/cpu-exec.c      | 35 +++++++++++++++++++++++++----------
 cpu-target.c              |  7 +++++--
 5 files changed, 34 insertions(+), 13 deletions(-)

Patch

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b1d76d6985..e1c798b07d 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -22,6 +22,7 @@ 
 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
 #define EXCP_YIELD      0x10004 /* cpu wants to yield timeslice to another */
 #define EXCP_ATOMIC     0x10005 /* stop-the-world and emulate atomic */
+#define EXCP_SINGLESTEP 0x10006 /* singlestep without debugging */
 
 void cpu_exec_init_all(void);
 void cpu_exec_step_atomic(CPUState *cpu);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fb397cdfc5..e3c8450f8f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1072,6 +1072,7 @@  void qemu_init_vcpu(CPUState *cpu);
 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
+#define SSTEP_NODEBUG 0x8  /* Single-stepping is not for debugging */
 
 /**
  * cpu_single_step:
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 863a84edf8..961cd9927a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -57,7 +57,8 @@  static inline bool excp_is_internal(int excp)
         || excp == EXCP_HALTED
         || excp == EXCP_EXCEPTION_EXIT
         || excp == EXCP_KERNEL_TRAP
-        || excp == EXCP_SEMIHOST;
+        || excp == EXCP_SEMIHOST
+        || excp == EXCP_SINGLESTEP;
 }
 
 /*
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 8b773d8847..6b4e63e69e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -349,7 +349,7 @@  static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc,
      * so that one could (gdb) singlestep into the guest kernel's
      * architectural breakpoint handler.
      */
-    if (cpu->singlestep_enabled) {
+    if (cpu->singlestep_enabled && !(cpu->singlestep_enabled & SSTEP_NODEBUG)) {
         return false;
     }
 
@@ -529,7 +529,11 @@  cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
      * is handled in cpu_handle_exception.
      */
     if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
-        cpu->exception_index = EXCP_DEBUG;
+        if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) {
+            cpu->exception_index = EXCP_DEBUG;
+        } else {
+            cpu->exception_index = EXCP_SINGLESTEP;
+        }
         cpu_loop_exit(cpu);
     }
 
@@ -781,13 +785,20 @@  static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
         cpu->exception_index = -1;
 
         if (unlikely(cpu->singlestep_enabled)) {
-            /*
-             * After processing the exception, ensure an EXCP_DEBUG is
-             * raised when single-stepping so that GDB doesn't miss the
-             * next instruction.
-             */
-            *ret = EXCP_DEBUG;
-            cpu_handle_debug_exception(cpu);
+            if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) {
+                /*
+                 * After processing the exception, ensure an EXCP_DEBUG is
+                 * raised when single-stepping so that GDB doesn't miss the
+                 * next instruction.
+                 */
+                *ret = EXCP_DEBUG;
+                cpu_handle_debug_exception(cpu);
+            } else {
+                /*
+                 * In case of non-debug single step, just return
+                 */
+                *ret = EXCP_SINGLESTEP;
+            }
             return true;
         }
     } else if (!replay_has_interrupt()) {
@@ -892,7 +903,11 @@  static inline bool cpu_handle_interrupt(CPUState *cpu,
                  * next instruction.
                  */
                 if (unlikely(cpu->singlestep_enabled)) {
-                    cpu->exception_index = EXCP_DEBUG;
+                    if (!(cpu->singlestep_enabled & SSTEP_NODEBUG)) {
+                        cpu->exception_index = EXCP_DEBUG;
+                    } else {
+                        cpu->exception_index = EXCP_SINGLESTEP;
+                    }
                     bql_unlock();
                     return true;
                 }
diff --git a/cpu-target.c b/cpu-target.c
index 667688332c..6293477ed9 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -322,9 +322,12 @@  void list_cpus(void)
    CPU loop after each instruction */
 void cpu_single_step(CPUState *cpu, int enabled)
 {
-    if (cpu->singlestep_enabled != enabled) {
-        cpu->singlestep_enabled = enabled;
+    int previous = cpu->singlestep_enabled;
+    bool prev_debug_en = previous && !(previous & SSTEP_NODEBUG);
+    bool cur_debug_en = enabled && !(enabled & SSTEP_NODEBUG);
 
+    cpu->singlestep_enabled = enabled;
+    if (prev_debug_en != cur_debug_en) {
 #if !defined(CONFIG_USER_ONLY)
         const AccelOpsClass *ops = cpus_get_accel();
         if (ops->update_guest_debug) {