diff mbox series

[v3,08/28] hw/intc/aspeed: Add support for multiple output pins in INTC

Message ID 20250213033531.3367697-9-jamin_lin@aspeedtech.com (mailing list archive)
State New
Headers show
Series Support AST2700 A1 | expand

Commit Message

Jamin Lin Feb. 13, 2025, 3:35 a.m. UTC 
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.

Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" function to connect source
orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize"
function to initialize output pins.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast27x0.c       | 6 +++++-
 hw/intc/aspeed_intc.c         | 4 ++++
 include/hw/intc/aspeed_intc.h | 5 +++--
 3 files changed, 12 insertions(+), 3 deletions(-)

Comments

Cédric Le Goater Feb. 18, 2025, 5:53 a.m. UTC | #1 
On 2/13/25 04:35, Jamin Lin wrote:
> Added support for multiple output pins in the INTC controller to
> accommodate the AST2700 A1.
> 
> Introduced "num_outpins" to represent the number of output pins. Updated the
> IRQ handling logic to initialize and connect output pins separately from input
> pins. Modified the "aspeed_soc_ast2700_realize" function to connect source
> orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize"
> function to initialize output pins.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

could you please add to the .git/config file :

     [diff]
         orderFile = /path/to/qemu/scripts/git.orderfile

This will put .h files before the .c files in the patch.


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/arm/aspeed_ast27x0.c       | 6 +++++-
>   hw/intc/aspeed_intc.c         | 4 ++++
>   include/hw/intc/aspeed_intc.h | 5 +++--
>   3 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 18e14a7914..775e953afd 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -519,10 +519,14 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>       aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
>                       sc->memmap[ASPEED_DEV_INTC]);
>   
> -    /* GICINT orgates -> INTC -> GIC */
> +    /* source orgates -> INTC */
>       for (i = 0; i < ic->num_inpins; i++) {
>           qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
>                                   qdev_get_gpio_in(DEVICE(&a->intc), i));
> +    }
> +
> +    /* INTC -> GIC128 - GIC136 */
> +    for (i = 0; i < ic->num_outpins; i++) {
>           sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
>                              qdev_get_gpio_in(DEVICE(&a->gic),
>                                   aspeed_soc_ast2700_gic_intcmap[i].irq));
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 95b40e1935..32c4a3bb44 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -354,6 +354,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
>           if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
>               return;
>           }
> +    }
> +
> +    for (i = 0; i < aic->num_outpins; i++) {
>           sysbus_init_irq(sbd, &s->output_pins[i]);
>       }
>   }
> @@ -389,6 +392,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
>       dc->desc = "ASPEED 2700 INTC Controller";
>       aic->num_lines = 32;
>       aic->num_inpins = 9;
> +    aic->num_outpins = 9;
>       aic->mem_size = 0x4000;
>       aic->reg_size = 0x2000;
>   }
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 5f0429c7f9..0bf96a81bb 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -17,8 +17,8 @@
>   OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>   
>   #define ASPEED_INTC_NR_REGS (0x2000 >> 2)
> -#define ASPEED_INTC_NR_INTS 9
>   #define ASPEED_INTC_MAX_INPINS 9
> +#define ASPEED_INTC_MAX_OUTPINS 9
>   
>   struct AspeedINTCState {
>       /*< private >*/
> @@ -30,7 +30,7 @@ struct AspeedINTCState {
>   
>       uint32_t regs[ASPEED_INTC_NR_REGS];
>       OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
> -    qemu_irq output_pins[ASPEED_INTC_NR_INTS];
> +    qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
>   
>       uint32_t enable[ASPEED_INTC_MAX_INPINS];
>       uint32_t mask[ASPEED_INTC_MAX_INPINS];
> @@ -42,6 +42,7 @@ struct AspeedINTCClass {
>   
>       uint32_t num_lines;
>       uint32_t num_inpins;
> +    uint32_t num_outpins;
>       uint64_t mem_size;
>       uint64_t reg_size;
>       const MemoryRegionOps *reg_ops;
Jamin Lin Feb. 21, 2025, 1:31 a.m. UTC | #2 
Hi Cedric, 

> Subject: Re: [PATCH v3 08/28] hw/intc/aspeed: Add support for multiple output
> pins in INTC
> 
> On 2/13/25 04:35, Jamin Lin wrote:
> > Added support for multiple output pins in the INTC controller to
> > accommodate the AST2700 A1.
> >
> > Introduced "num_outpins" to represent the number of output pins.
> > Updated the IRQ handling logic to initialize and connect output pins
> > separately from input pins. Modified the "aspeed_soc_ast2700_realize"
> > function to connect source orgates to INTC and INTC to GIC128 - GIC136.
> Updated the "aspeed_intc_realize"
> > function to initialize output pins.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> 
> could you please add to the .git/config file :
> 
Thank you for letting me know this information and for your suggestion.
I will add it to my local Git configuration.
Jamin

>      [diff]
>          orderFile = /path/to/qemu/scripts/git.orderfile
> 
> This will put .h files before the .c files in the patch.
> 
> 
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
> 
> Thanks,
> 
> C.
> 
> 
> > ---
> >   hw/arm/aspeed_ast27x0.c       | 6 +++++-
> >   hw/intc/aspeed_intc.c         | 4 ++++
> >   include/hw/intc/aspeed_intc.h | 5 +++--
> >   3 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 18e14a7914..775e953afd 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -519,10 +519,14 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> >       aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
> >                       sc->memmap[ASPEED_DEV_INTC]);
> >
> > -    /* GICINT orgates -> INTC -> GIC */
> > +    /* source orgates -> INTC */
> >       for (i = 0; i < ic->num_inpins; i++) {
> >           qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
> >
> qdev_get_gpio_in(DEVICE(&a->intc),
> > i));
> > +    }
> > +
> > +    /* INTC -> GIC128 - GIC136 */
> > +    for (i = 0; i < ic->num_outpins; i++) {
> >           sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
> >                              qdev_get_gpio_in(DEVICE(&a->gic),
> >
> > aspeed_soc_ast2700_gic_intcmap[i].irq));
> > diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index
> > 95b40e1935..32c4a3bb44 100644
> > --- a/hw/intc/aspeed_intc.c
> > +++ b/hw/intc/aspeed_intc.c
> > @@ -354,6 +354,9 @@ static void aspeed_intc_realize(DeviceState *dev,
> Error **errp)
> >           if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
> >               return;
> >           }
> > +    }
> > +
> > +    for (i = 0; i < aic->num_outpins; i++) {
> >           sysbus_init_irq(sbd, &s->output_pins[i]);
> >       }
> >   }
> > @@ -389,6 +392,7 @@ static void aspeed_2700_intc_class_init(ObjectClass
> *klass, void *data)
> >       dc->desc = "ASPEED 2700 INTC Controller";
> >       aic->num_lines = 32;
> >       aic->num_inpins = 9;
> > +    aic->num_outpins = 9;
> >       aic->mem_size = 0x4000;
> >       aic->reg_size = 0x2000;
> >   }
> > diff --git a/include/hw/intc/aspeed_intc.h
> > b/include/hw/intc/aspeed_intc.h index 5f0429c7f9..0bf96a81bb 100644
> > --- a/include/hw/intc/aspeed_intc.h
> > +++ b/include/hw/intc/aspeed_intc.h
> > @@ -17,8 +17,8 @@
> >   OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass,
> ASPEED_INTC)
> >
> >   #define ASPEED_INTC_NR_REGS (0x2000 >> 2) -#define
> > ASPEED_INTC_NR_INTS 9
> >   #define ASPEED_INTC_MAX_INPINS 9
> > +#define ASPEED_INTC_MAX_OUTPINS 9
> >
> >   struct AspeedINTCState {
> >       /*< private >*/
> > @@ -30,7 +30,7 @@ struct AspeedINTCState {
> >
> >       uint32_t regs[ASPEED_INTC_NR_REGS];
> >       OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
> > -    qemu_irq output_pins[ASPEED_INTC_NR_INTS];
> > +    qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
> >
> >       uint32_t enable[ASPEED_INTC_MAX_INPINS];
> >       uint32_t mask[ASPEED_INTC_MAX_INPINS]; @@ -42,6 +42,7 @@
> struct
> > AspeedINTCClass {
> >
> >       uint32_t num_lines;
> >       uint32_t num_inpins;
> > +    uint32_t num_outpins;
> >       uint64_t mem_size;
> >       uint64_t reg_size;
> >       const MemoryRegionOps *reg_ops;
diff mbox series

Patch

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 18e14a7914..775e953afd 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -519,10 +519,14 @@  static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
                     sc->memmap[ASPEED_DEV_INTC]);
 
-    /* GICINT orgates -> INTC -> GIC */
+    /* source orgates -> INTC */
     for (i = 0; i < ic->num_inpins; i++) {
         qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
                                 qdev_get_gpio_in(DEVICE(&a->intc), i));
+    }
+
+    /* INTC -> GIC128 - GIC136 */
+    for (i = 0; i < ic->num_outpins; i++) {
         sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
                            qdev_get_gpio_in(DEVICE(&a->gic),
                                 aspeed_soc_ast2700_gic_intcmap[i].irq));
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 95b40e1935..32c4a3bb44 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -354,6 +354,9 @@  static void aspeed_intc_realize(DeviceState *dev, Error **errp)
         if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
             return;
         }
+    }
+
+    for (i = 0; i < aic->num_outpins; i++) {
         sysbus_init_irq(sbd, &s->output_pins[i]);
     }
 }
@@ -389,6 +392,7 @@  static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
     dc->desc = "ASPEED 2700 INTC Controller";
     aic->num_lines = 32;
     aic->num_inpins = 9;
+    aic->num_outpins = 9;
     aic->mem_size = 0x4000;
     aic->reg_size = 0x2000;
 }
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 5f0429c7f9..0bf96a81bb 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,8 +17,8 @@ 
 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
 
 #define ASPEED_INTC_NR_REGS (0x2000 >> 2)
-#define ASPEED_INTC_NR_INTS 9
 #define ASPEED_INTC_MAX_INPINS 9
+#define ASPEED_INTC_MAX_OUTPINS 9
 
 struct AspeedINTCState {
     /*< private >*/
@@ -30,7 +30,7 @@  struct AspeedINTCState {
 
     uint32_t regs[ASPEED_INTC_NR_REGS];
     OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
-    qemu_irq output_pins[ASPEED_INTC_NR_INTS];
+    qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
 
     uint32_t enable[ASPEED_INTC_MAX_INPINS];
     uint32_t mask[ASPEED_INTC_MAX_INPINS];
@@ -42,6 +42,7 @@  struct AspeedINTCClass {
 
     uint32_t num_lines;
     uint32_t num_inpins;
+    uint32_t num_outpins;
     uint64_t mem_size;
     uint64_t reg_size;
     const MemoryRegionOps *reg_ops;